Method to reduce stacking fault nucleation sites and reduce...

Etching a substrate: processes – Gas phase etching of substrate – Application of energy to the gaseous etchant or to the...

Reexamination Certificate

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C438S507000, C438S692000, C438S745000, C438S931000, C216S038000, C216S083000, C216S090000, C134S001200, C134S001300, C117S951000

Reexamination Certificate

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07018554

ABSTRACT:
A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and sub-surface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.

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