Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2009-08-12
2010-12-21
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S184000, C438S230000, C438S267000, C438S303000, C438S304000, C438S446000, C438S592000, C438S595000
Reexamination Certificate
active
07855135
ABSTRACT:
A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
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Chang Leland
Lauer Isaac
Mo Renee T.
Sleight Jeffrey W.
Harrington & Smith
International Business Machines - Corporation
Jung Michael
Richards N Drew
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