Method to reduce overhead associated with system I/O in a...

Details Method to reduce overhead associated with system I/O in a... Method to reduce overhead associated with system I/O in a...

2000-06-16

2003-12-02

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

C711S006000, C711S163000, C711S203000, C711S206000, C709S241000, C709S241000, C710S006000

Reexamination Certificate

active

06658522

ABSTRACT:

FIELD OF INVENTION
The present invention relates to operating systems for multi-processor computer systems and more particularly to a system and method for an input/output (I/O) operation of a multi-processor computer system, more specifically a system and method for an I/O operation in which a system wide global PFD lock is not a requisite to performing the I/O operation.
BACKGROUND OF THE INVENTION
Many current computer systems employ a multi-processor configuration that includes two or more processing units interconnected by a bus system and each being capable of independent or cooperative operation. Such a multi-processor configuration increases the total system processing capability and allows the concurrent execution of multiple related or separate tasks by assigning each task to one or more processors. Such systems also typically include a plurality of mass storage units, such as disk drive devices to provide adequate storage capacity for the number of task executing on the systems.
One type of multi-processor computer system embodies a symmetric multiprocessing (SMP) computer architecture which is well known in the art as overcoming the limitations of single or uni-processors in terms of processing speed and transaction throughput, among other things. Typical, commercially available SMP systems are generally “shared memory” systems, characterized in that multiple processors on a bus, or a plurality of busses, share a single global memory or shared memory. In shared memory multiprocessors, all memory is uniformly accessible to each processor, which simplifies the task of dynamic load distribution. Processing of complex tasks can be distributed among various processors in the multiprocessor system while data used in the processing is substantially equally available to each of the processors undertaking any portion of the complex task. Similarly, programmers writing code for typical shared memory SMP systems do not need to be concerned with issues of data partitioning, as each of the processors has access to and shares the same, consistent global memory.
There is shown in
FIG. 3
a block diagram of an exemplary multiprocessor system that implements a SMP architecture. For further details regarding this system, reference shall be made to U.S. Ser. No. 09/309,012, filed Sep. 3, 1999, the teachings of which are incorporated herein by reference.
Another computer architecture known in the art for use in a multi-processor environment is the Non-Uniform Memory Access (NUMA) architecture or the Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture, which are known in the art as being an extension of SMP but which supplants SMPs “shared memory architecture.” NUMA and CCNUMA architectures are typically characterized as having distributed global memory. Generally, NUMA/CCNUMA machines consist of a number of processing nodes connected through a high bandwidth, low latency interconnection network. The processing nodes are each comprised of one or more high-performance processors, -associated cache, and a portion of a global shared memory. Each node or group of processors has near and far memory, near memory being resident on the same physical circuit board, directly accessible to the node's processors through a local bus, and far memory being resident on other nodes and being accessible over a main system interconnect or backbone. Cache coherence, i.e. the consistency and integrity of shared data stored in multiple caches, is typically maintained by a directory-based, write-invalidate cache coherency protocol, as known in the art. To determine the status of caches, each processing node typically has a directory memory corresponding to its respective portion of the shared physical memory. For each line or discrete addressable block of memory, the directory memory stores an indication of remote nodes that are caching that same line.
There is shown in
FIG. 4
a high level block diagram of another exemplary multiprocessor system but which implements a CCNUMA architecture. For further details regarding this system, reference shall be made to U.S. Pat. No. 5,887,146, the teachings of which are incorporated herein by reference.
Almost all modern computer systems, including multi-processor system employing the above-described computer architectures, use Virtual Memory, in which addressable ranges of computer memory may or may not be present in, or connected to, equivalent physical memory at any given time. It is the responsibility of the operating system, or computer hardware, to ensure that the Virtual Memory be mapped, or connected, to corresponding physical memory when the Virtual Memory is being accessed by either an executing processor or other device (usually an I/O device). Virtual Memory that is not currently being accessed is free to be “unmapped”, or disconnected from its corresponding physical memory. The contents of the Virtual Memory that is unmapped or disconnected are generally maintained in a so-called “backing store” (usually a disk drive).
Because of the asynchronous nature of I/O operations, it is vitally important that the Virtual Memory involved with the I/O operation is not unmapped in the time between the initiation of an I/O operation (such as a read, or input, from a disk device), and the completion of the same I/O operation (such as the actual storing into memory of the retrieved disk device data). Thus, it is necessary for Virtual Memory pages involved in an I/O operation, to be “locked”, “wired”, or “pinned”, to their corresponding physical memory during the entire time that data is moving between the physical memory and the I/O device. In this way, the pinned pages of physical memory cannot be unmapped during the I/O operation.
There are two techniques that have been implemented for ensuring the proper mapping of virtual memory to physical memory for I/O operations. The first and simplest method, and the technique generally being implemented, in general terms involves individually querying the status of each and every physical memory page participating in the I/O operation, ensuring it is “paged in”, “marked as locked”, “pinned”, or “wired”, processing the I/O operation, individually unlocking each physical memory page, and exiting the I/O operation. This solution is expensive and inefficient in that it typically requires the operating system to obtain exclusive access to the physical memory control structures through a broad-based system lock, such as a spinlock.
More specifically, there is shown in
FIG. 1A
a flow diagram of the high level process for implementing an I/O operation according to the first technique in a computer system employing two or more processors, where the physical memory can be a shared global memory as with SMP architectures or a distributed global memory as with NUMA/CCNUMA architectures. In accordance with this technique, when a program or process running on one or more processors requires information, for example, to be read to the physical memory from a storage device, written to a storage device from the physical memory or outputted from the physical memory to a communications device or network, an I/O request is made by the processor to the operating system. Pursuant to this request, the operating system initiates an I/O operation, Step
100
. As discussed hereinafter, the initiation of the I/O operation can be delayed because of other ongoing activities.
Once the I/O operation is initiated, the operating system proceeds to ensure that the physical memory pages are pinned, STEP
102
. As is known in the art, physical memory is typically subdivided into pages, these pages can be mapped or pinned individually so as to correspond to pages or addresses of the Virtual Memory for a given application. This pinning process ensures that the page frame database (PFD) for the physical memory is arranged so as to lock each page of physical memory corresponding to the virtual memory pages or addresses to be read/inputted to or written/outputted from. The PFD covers or describes all of the physical memory of a given machine or co

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