Method to reduce MOL damage on NiSi

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S651000, C438S682000, C257SE21636

Reexamination Certificate

active

07994038

ABSTRACT:
Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.

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patent: 2005/0247926 (2005-11-01), Sun et al.
patent: 2006/0051961 (2006-03-01), Cabral et al.
patent: 2006/0284263 (2006-12-01), Chang et al.
patent: 2007/0093047 (2007-04-01), Okuno et al.
patent: 2009/0127594 (2009-05-01), Arunachalam et al.

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