Method to reduce lot-to-lot variation of array threshold...

Details Method to reduce lot-to-lot variation of array threshold... Method to reduce lot-to-lot variation of array threshold...

2001-08-13

2003-10-14

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S109000, C700S029000, C700S031000, C438S005000, 43

Reexamination Certificate

active

06633793

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method to reduce lot-to-lot variation in a DRAM device, and more particularly, to a method to reduce lot-to-lot variation of array voltage threshold (V
t
) by optimal selection of a process recipe in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
DRAM memory circuits are a basic building block in many electronic systems. A DRAM memory contains an array of densely-packed transistors with each transistor containing a charge storage capacitor. Precise control of the voltage threshold (V
t
) of the array transistors is critical to producing quality DRAM circuits. Unfortunately, technology shrinkage makes the V
t
value more difficult to control because lot-to-lot variations in any of several processing parameters can cause substantial variation in the V
t
value.
Referring now to
FIG. 1
, a top view of a section of a prior art DRAM memory circuit is shown. In this view, an active area
20
is formed in the semiconductor substrate. Gate conductor lines
24
are patterned such that they overlie the active area
20
to thereby form transistors. Deep trenches
28
are etched into the semiconductor substrate for deep trench capacitor storage nodes. A bit line contact
32
is made to provide connectivity between the active area
20
and the bit line, not shown.
Referring now to
FIG. 2
, a cross section of the prior art DRAM cell is shown. Note particularly that the deep trenches
28
are formed adjacent to the source and drain regions
38
. Shallow trench isolations (STI)
27
define the non-active areas. Sidewall spacers
36
and a capping layer
40
are used to complete the transistor gates formed by the gate conductor lines
24
. The bit line contact opening
32
through the overlying insulating layer
44
allows the bit line metal
48
to electrically contact the active area
38
.
It is important to note that several features in the prior art DRAM cell could potentially affect the V
t
value for the device. It is found, for example, that variation in the width of the active area
20
critical dimension, also called the active area CD, can cause variation in the V
t
value.
Several prior art approaches disclose methods or apparatus for controlling, monitoring, or modeling manufacturing processes for integrated circuits. U.S. Pat. No. 5,862,054 to Li teaches a method to collect, display, and archive statistical process control (SPC) data. A manufacturing information system (MIS) is used for data storage and retrieval. The SPC system monitors, but does not control, the manufacturing process. U.S. Pat. No. 6,061,640 to Tanaka et al teaches a method and an apparatus to analyze manufacturing data. Processing data and product data are analyzed using a multistage, multivariate analysis unit. Abnormal factors are extracted. The method provides a quality analysis tool but does not control the manufacturing process. U.S. Pat. No. 5,850,339 to Giles discloses a data analysis technique for optimizing a set of independent variables to best achieve a desired set of dependent variables. An iterative scoring system is disclosed wherein a high score indicates improved optimization. U.S. Pat. No. 5,841,676 to Ali et al teaches a system and a method to estimate the change point time in a manufacturing process under SPC. An exponential weighted moving average (EWMA) is used to detect a change point time. A diagnostic analysis is used to identify sources of process change. U.S. Pat. No. 5,727,128 to Morrison discloses a system and a method to automatically determine which process variables should be included in a process model. The method uses a regression analysis on the set of potential model input variables and then selects the variables to use based on a selection criteria. However, the method does not provide manufacturing process control.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a very manufacturable method to reduce variation in an output parameter in the manufacture of an integrated circuit device.
A further object of the present invention is to reduce lot-to-lot output parameter variation by optimally selecting a processing recipe based on parametric value measurements.
A yet further object is to select an optimal processing recipe by calculating a predicted output parameter value and then shifting the target processing recipe value to compensate for the predicted variation.
Another further object of the present invention is to reduce the threshold voltage variation of a DRAM array by compensating the source/drain ion implantation recipe based on a threshold voltage prediction calculation.
In accordance with the objects of this invention, a new method to reduce variation in an output parameter by selection of an optimal process recipe in the manufacture of an integrated circuit device is achieved. The method may be used to reduce the array voltage threshold in a DRAM circuit by compensating the source/drain ion implantation by calculating the predicted array voltage threshold. The integrated circuit device wafer is measured to obtain a present set of process parameter values. A predicted value of an output parameter is calculated by evaluating a first equation at the present set of process parameter values. The first equation is derived from a plurality of previous sets of process parameter values and the corresponding plurality of sets of output parameter values. An output parameter delta is calculated. The output parameter delta is the difference between the predicted value of the output parameter and a target value of the output parameter. A process recipe offset is calculated by evaluating a second equation at the output parameter delta. The second equation is derived from the plurality of selectable process recipes and the plurality of corresponding output parameter values. An optimal process recipe is selected from the plurality of selectable process recipes by adding the process recipe offset to the target process recipe to compensate the output parameter and to thereby reduce the variation of the output parameter in the manufacture of the integrated circuit device.


REFERENCES:
patent: 5408405 (1995-04-01), Mozumder et al.
patent: 5721152 (1998-02-01), Jenq et al.
patent: 5727128 (1998-03-01), Morrison
patent: 5841676 (1998-11-01), Ali et al.
patent: 5850339 (1998-12-01), Giles
patent: 5858825 (1999-01-01), Alsmeier et al.
patent: 5862054 (1999-01-01), Li
patent: 6061640 (2000-05-01), Tanaka et al.
patent: 6213848 (2001-04-01), Campbell et al.
patent: 6415193 (2002-07-01), Betawar et al.

Affiliated with

Also associated with

Rating

Method to reduce lot-to-lot variation of array threshold... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to reduce lot-to-lot variation of array threshold..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to reduce lot-to-lot variation of array threshold... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3173135