Method to reduce capacitance between metal lines

Details Method to reduce capacitance between metal lines Method to reduce capacitance between metal lines

2001-07-25

2002-06-11

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S624000, C438S625000, C438S631000, C438S638000

Reexamination Certificate

active

06403461

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce device capacitance presented by dielectric material located between metal lines.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, have allowed fabrication costs to be reduced as a result of obtaining a greater number of smaller semiconductor chips from a specific size starting semiconductor wafer, however with the smaller semiconductor chips still featuring performance equal to or greater than larger counterpart semiconductor chips, formed using larger features. However in some cases the use of smaller device features can deleteriously influence device performance in regards to increased resistance—capacitance (RC), delays. One such example is presented by the decreased spacing between metal interconnect structures is higher capacitance, when compared to the capacitance observed for devices formed with larger spaces between metal lines. The use of dielectric layers, with lower dielectric constants, thus lower capacitance, can be used in the narrowing spaces between metal lines, however these type of dielectric layers can present other problems, such as difficulties in deposition mode or poor conformality.
This invention will describe a novel procedure used to decrease device capacitance, specifically occurring as a result of the narrow spaces between metal lines, in terms of providing an air gap located in a portion of the dielectric layer used in the space between metal lines. Prior art, such as Yew et al, in U.S. Pat. No. 6,159,845, describe a process for an air gap between metal structures, however that prior art, unlike the present invention, has to use an overlying insulator layer, a planarization procedure, and photolithographic and etching procedures, to expose portions of the surface of the metal lines.
SUMMARY OF THE INVENTION
It is an object of this invention to decrease the capacitance of the dielectric material located in the narrow spaces between metal lines.
It is another object of this invention to decrease the capacitance of the dielectric material located in the narrow spaces between metal lines by forming an air gap in the portion of dielectric material located in the space between the metal lines.
It is still another object of this invention to form the air gap in the portion of dielectric material located in the space between the metal lines by depositing a low dielectric constant layer, using a mode of deposition with poor conformality characteristics, thus resulting in pinching of the thick portions of dielectric layer deposited on the sides of top portions of the metal lines, and leaving an air gap in the space between the thinner portions of dielectric layer formed on the sides of bottom portions of the metal lines.
In accordance with the present invention a process for forming a dielectric layer for passivation of metal lines, featuring an air gap formed in a portion of the dielectric layer located in a narrow space between metal lines, has been developed. After deposition of a thin silicon nitride layer on an underlying lower level metal interconnect structure, a composite insulator layer is deposited. Dual damascene openings are next formed in a composite insulator layer, and in the thin silicon nitride layer, with each dual damascene opening comprised of an overlying trench shape component, and an underlying, narrower in width, via opening component. After formation of metal structures in the dual damascene openings, the composite insulator layer surrounding the metal structures is selectively removed, exposing a portion of the thin silicon nitride layer located between the damascene type metal structures. A low dielectric constant layer is then deposited using a mode of deposition characterized by poor conformality features. Deposition of the dielectric layer on the sides of the wide component of the dual damascene type, metal structure, results in pinching, or closure of the narrow space between the wide components of the metal structures, completing the dielectric passivation procedure. The same deposition procedure also results in deposition on the sides of the narrow component of the dual damascene type metal structures, however the larger space between these components, in addition to the poor coverage characteristics of the dielectric passivation procedure, results in a desired air gap in the portion of dielectric layer located between the narrow width components of the metal structures. Planarization procedures are then used to expose the top surface of the dual damascene, metal structures.


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