Method to provide low dielectric constant voids between...

Details Method to provide low dielectric constant voids between... Method to provide low dielectric constant voids between...

1999-07-16

2001-06-26

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Utilizing reflow

C438S761000

Reexamination Certificate

active

06251799

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more particularly, to a method to provide low dielectric voids between adjacent conducting lines in the manufacture of integrated circuits.
(2) Description of the Prior Art
Feature size reduction is essential for realizing increased device content and higher switching speeds on integrated circuits. Reducing the spacing between conducting lines in a circuit, however, can result in an increase in capacitive coupling and subsequent crosstalk between these lines. In a crosstalk situation, a voltage on one conductor can affect the voltage on another conductor. In the worst case, data signals on the conductive lines can become so corrupted that correct operation of the integrated circuit at high speed becomes impossible.
The amount of capacitive coupling between adjacent conductors is directly related to the dielectric constant of the material between the conductors. In addition, as the distance between the conductors is reduced, the capacitive coupling increases exponentially. Clearly, a key to manufacturing integrated circuits with very close conductive line spacings is to reduce the dielectric constant of the isolating material between adjacent conductive lines.
FIG. 1
illustrates the capacitive coupling problem in the prior art. A semiconductor substrate
10
is shown. This substrate represents all of the layers and devices formed underlying the first metal conductors
12
. The metal has been etched to form closely spaced metal conductors
12
(for example, a space of less than 0.5 microns). A first layer of plasma enhanced oxide (PEOX)
14
has been deposited overlying the first metal conductors and the substrate. The first PEOX layer
14
typically forms overhangs on the vertical sides of the first metal runners as shown. A layer of spin-on-glass (SOG)
16
has been deposited overlying the first PEOX layer
14
. A second PEOX layer
18
has been formed overlying the SOG layer
16
. A via is shown etched through layers
18
,
16
, and
14
to the upper surface of one of the first metal conductors
12
. A second metal layer
20
has been deposited and etched to define a contact to the first metal runner
12
. Finally, a passivation layer
26
has been deposited overlying the second metal layer
20
and the second PEOX layer
18
.
Specifically note the region
24
in the SOG layer
16
between the two metal conductors
12
. Capacitive coupling between the two metal lines
12
occurs through region
24
as the lines are routed in parallel across the surface of the substrate
10
. For standard SOG material, the dielectric constant (∈) will be greater than 4. In the paper, “Low Capacitance Multilevel Interconnection Using Low-∈ Organic Spin-On Glass for Quarter-Micron High-Speed ULSIs,” by Furusawa et al, for the 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 59-60, a low-∈SOG material is disclosed with a dielectric constant of 3.0. For the prior art method, the capacitance coupling can be reduced in this fashion but it is still too high.
In the paper IEEE 1996 0-7803-3216-4, “Effect of Air Gap on Measurement Accuracy of Dielectric Constant,” by Lou et al, the problem of air gaps between material and conductor in the measurement of dielectric constant is discussed. Air has a low dielectric constant (∈=1.0). It is shown in the paper that the presence of air gaps can significantly reduce measured dielectric constants. In an integrated circuit application, such an air gap could be purposefully used to fill a part of the space between adjacent metal lines. Such an air gap inclusion would then reduce the effective dielectric constant and the capacitive coupling between the metal lines.
Several prior art approaches attempt to reduce the capacitive coupling between adjacent metal traces or to address particular problems associated with voids formed in the SOG material. U.S. Pat. No. 5,599,745 to Reinberg et al teaches a method to form air voids between closely spaced adjacent conductive lines by applying low melting point materials above the conductive lines. The low melting point materials are heated to cause a sagging overhanging layer on the sidewalls of the conductive lines that will then seal over air voids between the conductors. U.S. Pat. No. 5,665,657 to Lee teaches a method to remove voids unintentionally formed in the SOG layer by using an etch and fill method. U.S. Pat. Nos. 5,192,715 and 5,119,164 to Silwa, Jr. et al teach a method to form interfacial lateral sidewall voids by depositing tungsten and SOG overlying conductive traces. U.S. Pat. No. 5,728,631 to Wang teaches a method to form low capacitance dielectric air gaps between adjacent metal lines by using an electrocyclotron resonance (ECR) etching and deposition technique. U.S. Pat. No. 5,641,712 to Grivna et al teaches the formation of air gaps between interconnect lines by using a sputter etch technique on a plasma oxide layer.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits in which voids are formed in the inter-metal dielectric layer between narrowly-spaced adjacent conductive lines.
A further object of the present invention is to provide a method of forming voids in an inter-metal dielectric layer between narrowly spaced adjacent conductive lines to reduce capacitive coupling.
A yet further object of the present invention is to provide a method of forming voids in an inter-metal dielectric layer between narrowly-spaced adjacent conductive lines while using conventional SOG material and equipment.
In accordance with the objects of this invention, a new method for fabricating an integrated circuit in which an inter-metal dielectric is formed to include voids between narrowly spaced conductive lines is achieved. This method reduces capacitive coupling between the conductive lines. A semiconductor substrate is provided having narrowly spaced first conductive lines. A first dielectric layer is formed overlying the first conductive lines and the substrate. A first coating of spin-on-glass is deposited in a water rich environment. Air voids are formed in the SOG layer between the spaced first conductive lines as the first SOG layer is deposited and hard baked. A second SOG coating is deposited, hard baked and cured. The SOG layer is then is etched back to planarize the surface. A second dielectric layer is formed overlying the SOG layer. Via openings are etched through the first and second dielectric layers and the SOG layer to the top surface of the first conductive lines. A second conductive layer is deposited filling the via openings and overlying the second dielectric layer. The second conductive layer is patterned and etched to define useful traces. A passivation layer is deposited overlying the metal layer and the interlevel dielectric. The integrated circuit is completed.


REFERENCES:
patent: 5119164 (1992-06-01), Sliwa, Jr. et al.
patent: 5192715 (1993-03-01), Sliwa, Jr. et al.
patent: 5270267 (1993-12-01), Ouellet
patent: 5599745 (1997-02-01), Reinberg
patent: 5641712 (1997-06-01), Grivna et al.
patent: 5665657 (1997-09-01), Lee
patent: 5728631 (1998-03-01), Wang
patent: 5792705 (1998-08-01), Wang et al.
Furusawa et al., “Low Capacitance Multilevel Interconnection Using Low-E Organic Spin-On Glass for Quarter-Micron High-Speed ULSIs” 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 59-60.
Luo et al., “Effect of Air Gap on Measurement Accuracy of Dielectric Constant”, IEEE 1996 0-7803-3216-4.

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