Method to produce high density memory cells and small spaces...

Details Method to produce high density memory cells and small spaces... Method to produce high density memory cells and small spaces...

1999-05-26

2001-12-11

Ashton, Rosemary (Department: 1752)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S325000, C430S316000, C438S639000, C438S637000

Reexamination Certificate

active

06329124

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a method for producing small space patterns via employment of a conformal nitride layer.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as comers and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photo mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The spacing between adjacent lines of an integrated circuit is an important dimension, and ever continuing efforts are made toward reducing such spacing dimension. The wavelength of light used in the photolithographic process along with the lithographic tool set employed in the process generally dictate the spacing dimension. For example, a tool set designed to provide lines and/or spaces at 0.18 &mgr;m does not achieve consistent lines and/or spacing at its minimum range of 0.18 &mgr;m but rather is employed to generate lines and/or spacing above the minimum range (e.g., 0.20 &mgr;m) with fairly consistent results.
In view of the above, it would be desirable for a technique which allows for a particular lithographic tool set to be employed and achieve consistent lines and/or spacing between lines at the minimum range of the tool set and even below the minimum range.
SUMMARY OF THE INVENTION
The present invention relates to a method for employing a photolithographic tool set and achieving substantially consistent spacing dimensions below the minimum range of the tool set. A given photolithographic tool set is employed to pattern a photoresist layer in a desired fashion. The tool set is capable of achieving a smallest spacing dimension between adjacent lines of d
1
. After the photoresist layer is patterned, an etch step is performed to etch the pattern in an underlying ARC layer. Next, a nitride layer is conformably deposited over the patterned ARC layer. Thereafter, a directional etch is performed to remove a particular amount of the nitride layer (preferably a thickness equivalent to the thickness of the nitride layer residing over an ARC portion). The directional etch leaves nitride sidewalls along the patterned ARC portions which result in a reduction in dimension size of exposed areas interposed between adjacent ARC portions. Thus a spacing dimension size (d
2
) of exposed areas is substantially less than the spacing dimension size (d
1
) of exposed areas prior to the depositing the nitride layer. An etch step is performed to etch layers underlying the ARC layer. Adjacent lines etched from one of the underlayers will have a smallest spacing design dimension of d
2
as compared to d
1
. Thus, the present invention provides for achieving spacing dimensions between lines at and below a minimum patterning range for a particular lithographic tool set.
One aspect of the invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d
1
is a smallest space dimension of an exposed area of an ARC layer underlying the photoresist layer. The ARC layer is etched. A nitride layer is formed to be conformal to the patterned ARC layer and exposed portions of an underlayer underlining the ARC layer. The nitride layer is etched to form nitride sidewalls, the nitride sidewalls reducing the smallest space dimension of the exposed underlayer area to d
2
, wherein d
2
<d
1
.
Another aspect of the invention relates to a method for producing a small space pattern in a semiconductor layer. A photoresist layer of a semiconductor structure is patterned with a photolithographic tool set, a minimum printed space dimension of the patterned photoresist being d
1
, wherein d
1
is the smallest space dimension consistently printable by the photolithographic tool set. A nitride layer is formed to be conformal to a patterned ARC layer underlying the photoresist layer and exposed portions as an underlayer underlying the ARC layer, d
1
being the smallest dimension of the exposed portions. The nitride layer is etched an amount substantially equivalent to a minimum thickness parameter (&ggr;) of the nitride to leave nitride sidewalls such that the smallest dimension of the exposed portions is now d
2
, wherein d
2
<d
1
.
Another aspect of the invention relates to method of forming closely spaced lines from a polysilicon layer. A semiconductor structure is used, the semiconductor structure including: the polysilicon layer; and a patterned anti-reflective coating (ARC) layer over the polysilicon layer, wherein a smallest dimension of at least one exposed portion of the polysilicon layer equals d
1
. A nitride layer is formed to conform to an exposed surface of the semiconductor structure. The nitride layer is etched so as to leave nitride portions along sidewalls of the ARC layer, the nitride portions reducing the smallest dimension of the at least one exposed portion of the polysilicon layer to d
2
, wherein d
2
<d
1
.
Still another aspect of the invention relates to a method of forming closely spaced lines from a polysilicon layer. A photolithographic tool set is used to pattern a photoresist layer of a semiconductor structure wherein d
1
is a smallest space dimension consistently printable by the photolithographic tool set, the semiconductor structure including: the polysilicon layer; an anti-reflective coating (ARC) layer over the polysilicon layer; and the patterned photoresist layer over the ARC layer, wherein a smallest dimension of at least one exposed portion of the ARC layer equals d
1
. The ARC layer is etched. The photoresist layer is removed. A nitride layer is formed to conform to remaining portions of the ARC layer and exposed portions of a polysilicon layer underlying the ARC layer. The nitride layer is etched so as to leave nitride sidewalls, the nitride sidewalls reducing the smallest dimension of the at least one exposed portion of the polysilicon layer to d
2
, wherein d
2
<d
1
The polysilicon layer is etched, wherein a smallest space dimension between at least two adjacent lines is substantially equal to d
2
.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description

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