Method to prevent silicide bubble in the VLSI process

Details Method to prevent silicide bubble in the VLSI process Method to prevent silicide bubble in the VLSI process

1994-10-05

1995-07-18

Quach, T. N.

Fishing, trapping, and vermin destroying

437200, 437239, 437247, 148DIG15, 148DIG147, H01L 21336, H01L 21283

Patent

active

054340969

ABSTRACT:
A method is described for fabricating an integrated circuit with polycide gate electrodes in which there is no delamination of the overlying dielectric layer. A polysilicon layer over a gate dielectric is provided on a silicon substrate. A silicide layer is formed over the polysilicon layer using WF.sub.6 and SiH.sub.4 as the reaction gases. The silicide and polysilicon layers are patterned to form polycide gate electrodes. The substrate is annealed initially in an inert gas atmosphere to remove excess fluorine gas, then in an oxygen atmosphere. Lightly doped source and drain ion implants are performed. Spacers are formed on the sidewalls of the polycide gate electrodes. Source/drain ion implants are performed with include fluoride ions. The substrate is degassed in an inert atmosphere to remove the excess fluoride ions. A dielectric layer is deposited over the pattern of polycide gate electrodes and flowed. There is no excess fluorine gas concentration to form a bubble in the dielectric layer. This completes fabrication of the polycide gate electrodes without delamination in the manufacture of an integrated circuit.

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