Method to prevent die attach adhesive contamination in...

Details Method to prevent die attach adhesive contamination in... Method to prevent die attach adhesive contamination in...

2000-11-01

2004-07-06

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S106000, C438S107000, C438S109000, C438S124000, C438S127000, C029S841000, C257S777000, C257S718000, C257S723000, C257S690000, C361S310000, C361S735000

Reexamination Certificate

active

06759307

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims foreign priority benefit to Singapore patent application, Serial No. 200005397-5, filed Sep. 21, 2000.
TECHNICAL FIELD
This invention relates generally to integrated circuit semiconductor device assemblies. More particularly, the present invention relates to stacked arrangements for semiconductor dice in semiconductor device assemblies.
BACKGROUND
Semiconductor devices are increasingly used in portable electronic applications, necessitating the development of smaller, higher-performance components. In conventional semiconductor manufacturing processes, a multitude of integrated circuit (IC) dice or semiconductor dice is typically fabricated at one time onto a wafer comprising a semiconducting substrate (e.g., silicon or gallium arsenide) through methods well known in the art. These semiconductor dice are then incorporated, in turn, into a system by mounting them on a carrier substrate, for example, a printed circuit board, to interconnect with the rest of the elements of the system, many of which are also other semiconductor dice.
In recent years, semiconductor manufacturing technology has steadily progressed, resulting in ever-increasing numbers of circuit elements placed on a single semiconductor die. Semiconductor wafers are now subjected to thinning processes, resulting in the removal of nearly all excess silicon from individual semiconductor dice. To further decrease the size of the overall packaged system, printed circuit boards and other component supporting substrates are made as small as practicable. For still further increases in electronics density, recent innovations have turned to new ways to package semiconductor dice. One such innovation involves vertically stacking a plurality of horizontally disposed semiconductor dice to form a dense electronic package. By using such stacking arrangements, multiple semiconductor dice can be attached to the system using the footprint area of a single semiconductor die. The resulting increases in density allow for faster signal propagation while providing lower overall device weight. Additionally, these “chip-on-chip or die-on-die” arrangements can often be fabricated faster and more cheaply than by designing new integrated circuitry for substrates.
The lack of available “real estate” on smaller circuit boards makes the stacking of semiconductor dice particularly desirable. One type of stacking arrangement, wherein several bare semiconductor dice used for the same or different functions are mounted in a common package, is known as a multi-chip module (MCM). MCMs generally contain a plurality of semiconductor dice in a dense arrangement where they are packaged together in a supporting substrate that can be hermetically sealed. Although prior art MCMs typically have a number of individual semiconductor dice mounted within the package in a laterally adjacent manner, the vertical stacking of semiconductor dice is increasingly gaining acceptance.
Many types of semiconductor dice can be used to form MCM chip-on-chip or die-on-die stacks, including dynamic random access memory (DRAM), static random access memory (SRAM) and FLASH memory chips, as well as semiconductor dice having other types of functions such as analog-to-digital convertor (ADC) semiconductor dice, microprocessors, and field programmable gate arrays (FPGAs). Typically, the stacked semiconductor dice have electrical contacts which are coupled in common or in parallel to contacts on the substrate board.
In early MCM stacking arrangements, single stacks of semiconductor dice were generally made using semiconductor dice having substantially equal dimensions. For example, in U.S. Pat. 5,323,060, assigned to the assignee of the present application, a plurality of identical, vertically stacked semiconductor dice is disclosed with a relatively thick adhesive layer interposed therebetween. The active circuitry of the horizontally disposed semiconductor dice is shown facing upwardly, with wirebonds from each semiconductor die extending downwardly from the active surface to contact pads onto a multi-chip module substrate.
In the case of memory semiconductor dice, vertical stacking proves particularly advantageous since a,plurality of semiconductor dice could be used to multiply the amount of memory available. Illustrative of the prior state of the art in this regard is “
Laminated Memory: A new
3-
Dimensional Packaging Technology for MCM”, Proceedings of
1994
IEEE Multi-Chip Module Conference
, pp. 58-63.
More recently, single stacks have been made comprised of semiconductor dice of different sizes and/or functions directly attached to one another. Generally, one or more semiconductor dice are bonded on top of a larger semiconductor die, although larger semiconductor dice have been placed on smaller semiconductor dice using various ball grid array connections and various interposers as shown in U.S. Pat. Nos. 5,977,640 and 5,790,384, respectively.
Numerous packaging alternatives for stacked dice are found in the art. In U.S. Pat. No. 5,777,345, an integrated circuit package is disclosed wherein a first semiconductor die (a microprocessor) is attached to a die paddle of a lead frame, and a second smaller semiconductor die (a memory chip) is directly attached to the upwardly facing active surface of the first semiconductor die. The bonding pads of the semiconductor dice are shown to be connected to each other, and to the lead frame, by a wire bonding process.
U.S. Pat. No. 5,998,884 discloses horizontally disposed bare semiconductor dice stacked atop one another in offset fashion such that an edge portion of each semiconductor die is exposed. On the edge portions of each semiconductor die are terminals (bond pads) for interconnection of the semiconductor dice to an interconnection substrate.
U.S. Pat. No. 6,005,778 shows semiconductor die stacking arrangements wherein a planar silicon spacer with a conductive surface and upwardly facing bond pads is mounted between two semiconductor dice on a substrate carrier. The planar conductive spacer is shown with two configurations. In a first configuration, the intermediately disposed spacer has a two-tiered portion at its lateral edges, with bond pads exposed on the lower of the two tiers. The spacer is further provided with lesser horizontal dimensions than the first semiconductor die, such that the two lateral edges of the first semiconductor die, containing bond pads for wire bonding to the substrate, remain exposed after the spacer is adhesively affixed to the first semiconductor die. In a second embodiment, the planar spacer has a larger footprint than the horizontally disposed semiconductor dice used in the assembly. The spacer is placed intermediate to the two smaller semiconductor dice such that lateral edge upper surface areas of the spacer, containing bond pads and wire bonds, extend beyond the footprints of both semiconductor dice. The second semiconductor die, also containing wire bonds on its upper surface lateral edges, is bonded to the spacer by an adhesive layer, leaving the bonding pads and wire bonds of the spacer exposed.
In these types of stacked semiconductor die arrangements, the semiconductor dice are typically bonded to each other, or to intermediately disposed spacers/interposers, by means of an adhesive layer. Typically, bare semiconductor dice are attached to such substrates using organic-based adhesives. The adhesive layer is typically dispensed automatically by screen printing, by a stamping device, or by a needle or syringe, in a non-cured state (soft phase), and is deposited in a predetermined area designated for the mounting of the semiconductor die (i.e., the die attach area). Meanwhile, the semiconductor die to be mounted is then typically picked up and held by an automated vacuum mechanism, or other apparatus, of a die bonding machine. The semiconductor die is then positioned over the center of the die attach area and is pressed into the previously deposited adhesive, ideally forming a uniform layer of adhesive under the semiconductor die.

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