Method to prevent delamination of spin-on-glass and plasma...

Details Method to prevent delamination of spin-on-glass and plasma... Method to prevent delamination of spin-on-glass and plasma...

1999-08-02

2001-02-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S782000, C438S766000

Reexamination Certificate

active

06184123

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of an interlevel dielectric comprised of a spin-on-glass and a plasma-enhanced silicon nitride stack.
(2) Description of the Prior Art
Spin-on-glass (SOG) is a material commonly used in the manufacture of integrated circuits as a dielectric or insulating layer. The advantage of SOG over other forms of dielectric material, such as low-pressure chemical vapor deposited silicon oxide (CVD), is that SOG can reliably fill and planarize even very difficult wafer surface topologies.
SOG is essentially a form of silicon oxide that is suspended in a solution of solvent. Typically, SOG is made from a silicate or a polysiloxane material dissolved in a combination of a low boiling point solvent, such as methanol, and a high boiling point solvent, such as butyl cellosolve. SOG is applied by dispensing a small amount of the solution onto a wafer that is spinning. Most of the solvent, or vehicle, is then driven off the wafer surface during a low-temperature drying step that is usually called the bake step. The process of coating and drying SOG layers may then be repeated until a sufficient amount of material has been built up to achieve the coverage and planarization desired. Once the layer of SOG is built up, a curing step is performed. During the curing step, the SOG is subjected to a high temperature environment to breakdown the silicate or the polysiloxane material to form a more nearly silicon dioxide material.
Once the SOG layer is formed, it is typical in the art to cover the SOG with a capping layer such as silicon oxide or silicon nitride before depositing conductive layers such as aluminum. It is the specific case of using plasma-enhanced silicon nitride as a capping layer for SOG that this invention is seeking to improve.
Referring to
FIG. 1
, a partially-completed prior art integrated circuit is shown in cross-section. A layer of thick field oxide
14
has been formed overlying a substrate
10
. Two conductive traces
18
are shown defined overlying the field oxide layer
14
. A layer of insulating oxide
22
has been deposited overlying the conductors. A thick layer of spin-on-glass
26
is shown overlying the insulating layer
22
. The SOG layer has been formed using the process of coating, drying, and curing outlined above. Finally, a layer of plasma-enhanced silicon nitride, or simply plasma nitride,
30
, has been deposited overlying the SOG layer
26
. Plasma nitride is commonly used as an insulating dielectric in integrated circuit manufacturing because it can be deposited with low pinhole density, has good mechanical properties, and a high dielectric constant when compared to silicon oxide.
A problem that occurs in the conventional art is also shown in FIG.
1
. Poor layer to layer adhesion between plasma nitride
30
and SOG
26
can cause delamination
35
to occur. Subsequent processing steps, such as polyimide coating and curing and even certain assembly processes can cause this delamination
35
that, in turn, can cause a reduction in wafer yield or an increase in reliability problems.
There are several prior art references to the effects of ion implantation into spin-on-glass and other thin film materials. In “Manufacturing Advancements in an Organic Process by Ar
+
Implantation,” by Berti and Farina, 1996 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 259-264, argon ion implantation into SOG is shown to break Si—CH
3
bonds leaving only Si—OH bonds. The density of the SOG material is increased and the absorption and outgassing effects in SOG are reduced. The article “Modification Effects in Ion-Implanted SiO
2
Spin-On-Glass,” by Moriya, Diamond, and Kalish, in The Journal of the Electrochemical Society, Vol. 140, No. 5, May 1993, pp. 1442-1449, describes material volume shrinkage and a greater than 50% reduction in HF etch rate of SiO
2
-based SOG when implanted with either silicon or phosphorous. In “Plasma Processes for Thin Film Surface Treatment,” by Mukkavilla, Pasco, Farooq, and Griffin, in the Proceedings of the IEEE Electronic Component and Technology Conference, 1990, 40
th
, Vol. 1, pp. 737-745, modification of polyimide surface characteristics, such as wetting and adhesion, is seen due to ion implantation.
Several other prior art approaches attempt to improve the performance of SOG by ion implantation., U.S. Pat. No. 5,459,086 to Yang teaches a process to eliminate outgassing from the SOG layer. An ion implantation is performed at a large tilt angle through the via opening to prevent via poisoning from the SOG layer. U.S. Pat. No. 5,496,776 to Chien et al teaches a method to implant ions into a spin-on-glass layer sufficient to cause structural changes in the complete depth of the cured material and to cause the material to become moisture sorption and outgassing resistant. U.S. Pat. No. 5,413,953 to Chien et al discloses a process to planarize an oxide layer using an ion implant and etch back sequence where spin-on-glass is used as a sacrificial implant layer. U.S. Pat. No. 5,192,697 to Leong discloses a method to cure SOG using ion implantation of argon to cause material heating. U.S. Pat. No. 5,429,990 to Liu et al teaches a method to improve planarity and to eliminate via poisoning in spin-on-glass by ion implanting through the complete thickness of the SOG layer after curing.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating the interlevel dielectric in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to prevent the delamination of the layer stack of plasma-enhanced silicon nitride overlying spin-on-glass that makes up the interlevel dielectric.
A still further object of the present invention is to provide a method to prevent the delamination of the layer stack by ion implantation of the spin-on-glass before depositing the silicon nitride layer.
In accordance with the objects of this invention, a new method of fabricating the interlevel dielectric has been achieved. An ion implantation is performed on the spin-on-glass layer before the deposition of the plasma-enhanced silicon nitride layer to improve the layer-to-layer adhesion and thereby eliminate delamination. Field oxide isolation regions are provided overlying a semiconductor substrate to isolate active device regions. Conductive traces are provided overlying the substrate. An insulating oxide layer is deposited overlying the conductive traces. A thick layer of spin-on-glass is coated overlying the insulating oxide layer. The spin-on-glass layer is low-temperature baked. An ion implantation is performed to form an amorphous, silicon-rich, adhesion layer at the surface of the spin-on-glass layer. The spin-on-glass is then high-temperature cured. A first plasma-enhanced silicon nitride layer is deposited overlying the spin-on-glass layer to complete the interlevel dielectric. Via openings are etched to expose the top surfaces of the conductive traces. A conductive layer is deposited overlying the plasma-enhanced silicon nitride layer and filling the via openings. The conductive layer is etched to define connective features. A second plasma-enhanced silicon nitride layer is deposited as a passivation layer, and the integrated circuit is completed.


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patent: 5366850 (1994-11-01), Chen et al.
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