Method to prevent degradation of low dielectric constant...

Details Method to prevent degradation of low dielectric constant... Method to prevent degradation of low dielectric constant...

1999-09-20

2001-12-18

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S638000, C438S687000

Reexamination Certificate

active

06331479

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the prevention of the degradation of dielectric material, due to photoresist ashing, in the formation of copper damascene interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Copper damascene interconnects are becoming increasingly common in the art of integrated circuit manufacture. Copper interconnects offer a significant advantage over traditional aluminum interconnects because of the lower resistivity of copper. Unfortunately, copper does not etch as easily as aluminum. This fact makes it difficult to fabricate copper interconnects using the traditional deposition and patterning techniques.
Damascene techniques allow copper to be used as the interconnect material. In damascene processes, trenches are first patterned into a dielectric material. Then copper is deposited overlying the dielectric material to fill the trenches. Finally, a polish down operation is performed to remove excess copper and to form the interconnect patterns within the confines of the trenches.
Referring to
FIG. 1
, a cross-section of a partially completed, self-aligned, dual damascene structure in a prior art integrated circuit device is shown. An isolation layer
14
overlies a semiconductor substrate
10
. A first copper interconnect
22
, isolated by a first barrier layer
18
, is formed through the isolation layer
14
. A passivation layer
26
is formed overlying the isolation layer
14
and the first copper interconnects
22
. A first dielectric layer
30
overlies the passivation layer
26
. An etch stopping layer
34
overlies the first dielectric layer
30
. A photoresist layer
38
overlies the etch stopping layer
34
. The photoresist layer
38
is patterned to form openings where vias are planned for the self-aligned, dual damascene interconnects.
Referring now to
FIG. 2
, the etch stopping layer
34
is etched through to expose the underlying first dielectric layer
30
. To completely etch the etch stopping layer
34
, some over-etching into the first dielectric layer
30
must occur.
Referring now to
FIG. 3
, the photoresist layer
38
is stripped away. The conventional processes used for stripping photoresist are photoresist ashing or reactive ion etching (RIE) ashing. In ashing processes, a plasma of oxygen radicals are generated to etch away the developed photoresist, either isotropically or anisotropically. Unfortunately, the oxygen radicals will also attack
46
the exposed first dielectric layer
30
. If an organic low dielectric constant material is used for the first dielectric layer
30
, the degradation
46
caused by the ashing process is particularly severe. In addition, a post-etch solvent cleaning is often performed. This cleaning operation can attack the exposed interface between the first dielectric layer
30
and etch stopping layer
34
.
Referring now to
FIG. 4
, a second dielectric layer
50
is deposited overlying the etch stopping layer
34
and the first dielectric layer
30
. Due to the previously discussed degradation of the first dielectric layer
30
in the opening of the etch stopping layer
34
, the second dielectric layer
50
fails to planarize. A cap layer
54
is deposited overlying the second dielectric layer
50
. The lack of planarization is shown
58
. In addition, the reaction of oxygen radicals in the ashing plasma with the dielectric layers can cause bowing of the trench sidewalls and via poisoning. Via poisoning results from oxidation of the sidewalls of the trenches etched in the organic low dielectric constant material. Moisture can then be trapped in the oxidized surface. During subsequent high temperature processing, such as barrier metal deposition, the trapped moisture outgasses and prevents proper adhesion of the barrier layer.
Several prior art approaches disclose methods to form dual damascene structures in the fabrication of integrated circuits. U.S. Pat. No. 5,882,996 to Dai discloses a process to etch dual damascene trenches where a stack of photoresist, anti-reflective coating, and photoresist is used to pattern the trenches. U.S. Pat. No. 5,708,303 to Jeng teaches a process to form damascene interconnects where a low dielectric constant material is formed between metal interconnects with high dielectric constant layers, both overlying and underlying the interconnects, to reduce cross-talk. U.S. Pat. No. 5,741,741 to Tseng discloses a process to make planar metal interconnects using dual damascene structures. A hard mask layer overlying a planar insulating layer is used with two photoresist layers to create the dual damascene trenches. U.S. Pat. No. 5,741,626 to Jain et al teaches a method to form damascene structures using tantalum nitride (Ta
3
N
5
) as an anti-reflective coating, etching stop, or diffusion barrier.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming dual damascene copper interconnects in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate damascene copper interconnects where degradation of the dielectric material due to photoresist ashing is eliminated.
A yet further object of the present invention is to prevent degradation of the dielectric material due to photoresist ashing by using two, dissimilar, etch stopping layers underlying the photoresist layer and overlying the dielectric material.
Another yet further object of the present invention is to prevent poor planarization of dielectric layers, trench bowing, and via poisoning due to photoresist ashing damage.
In accordance with the objects of this invention, a new method of fabricating dual damascene interconnects has been achieved. First copper interconnects are provided through an isolation layer overlying a semiconductor substrate. A passivation layer is deposited overlying the first copper interconnects and the isolation layer. A first dielectric layer is deposited overlying the passivation layer. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. The first etch stopping layer comprises a material that has a lower etch rate than the second etch stopping layer in a process used to etch the second etch stopping layer. A photoresist layer is deposited overlying the second etch stopping layer. The photoresist layer is patterned to define openings for planned via trenches. The second etch stopping layer is etched through to form a hard mask for the planned via trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals. A second dielectric layer is deposited overlying the second etch stopping layer and the first etch stopping layer. A first cap layer is deposited overlying the second dielectric layer. A second cap layer is deposited overlying the first cap layer. The second cap layer comprises a material that has a lower etch rate than the first cap layer in a process used to etch the first cap layer. An optional anti-reflective coating layer is deposited overlying the second cap layer. A photoresist layer is deposited overlying the anti-reflective coating layer. The photoresist layer is patterned to define openings for planned interconnect trenches. The second cap layer is etched through to form a hard mask for the planned interconnect trenches. The photoresist layer and the anti-reflective coating are stripped away by photoresist ashing where the first cap layer protects the second dielectric layer from damage due to the presence of oxygen radicals in the ashing step. The first cap layer, the second dielectric layer, the first etch stopping layer, and the first dielectric layer are etched through to complete the interconnect trenches and the via trenches. The second cap layer is etched aw

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