Method to pipeline write misses in shared cache multiprocessor s

Details Method to pipeline write misses in shared cache multiprocessor s Method to pipeline write misses in shared cache multiprocessor s

1996-09-04

1999-02-23

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, G06F 1208

Patent

active

058754687

ABSTRACT:
In a computer system having a number of nodes, wherein one of the nodes has a number of processors which share a single cache, a method of providing release consistent memory coherency. Initially, a write stream is divided into separate intervals or epochs at each cache, delineated by processor synch operations. When a write miss is detected, a counter corresponding to the current epoch is incremented. When the write miss globally completes, the same epoch counter is decremented. Synch operations issued to the cache stall the issuing processor until all epochs up to and including the epoch that the synch ended have no misses outstanding. Write cache misses complete from the standpoint of the cache when ownership and data are present. This allows the latency of writes operations to be partially hidden in any combination of shared cache (both hardware and software controlled), and multiple context processors. The epoch mechanism can be used to build release consistent multiprocessor systems in the presence of shared caches.

REFERENCES:
Chong et al., "Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors", Oct. 1995, pp. 1085-1099, IEEE.
Adve et al., "A Comparison of Entry Consistency and Lazy Release Consistency Implementations", 1996, pp. 26-37, IEEE.

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