Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-03
2003-02-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S014000, C438S129000
Reexamination Certificate
active
06523161
ABSTRACT:
FIELD OF INVENTION
Invention relates to design of integrated circuits and more particularly to a method for optimizing net lists using simultaneous placement optimization, logic function optimization and net buffering.
BACKGROUND OF INVENTION
Prior art methods use a mathematical expression to provide an analytical solution for simultaneous placement of logic functions and logic optimization. The solution of such a mathematical expression would lie in the continuous domain. Furthermore, mapping this solution into a valid placement and a valid implementation of each logic function can lead to loss of optimality.
Therefore, there is a need for a method that will overcome the deficiencies found in the prior art.
SUMMARY OF INVENTION
Invention discloses a method for the design and fabrication of integrated circuits to optimize signal timing and circuit performance.
The method simultaneously obtains a placement of logic functions, mapping of logic functions onto library elements and buffering of nets connecting the logic functions to optimize signal timing. Logic functions may be moved between bins and or may be optimized to obtain the best cost. A best buffering solution is also computed for each logic function's location and size.
REFERENCES:
patent: 4745084 (1988-05-01), Rowson et al.
patent: 5638291 (1997-06-01), Li et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5787010 (1998-07-01), Schaefer et al.
patent: 5953518 (1999-09-01), Sugasawara et al.
patent: 6080201 (2000-06-01), Hojat et al.
patent: 6192504 (2001-02-01), Pfluger et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6314547 (2001-11-01), Donath et al.
patent: 6334205 (2001-12-01), Iyer et al.
Gopalakrishnan Padmini
Raje Salil
Liu Andrea
Monterey Design Systems, Inc.
Smith Matthew
Vierra Magen Marcus Harmon & DeNiro LLP
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