Method to optimize effective page number to real page number...

Details Method to optimize effective page number to real page number... Method to optimize effective page number to real page number...

2005-02-09

2008-03-25

Sough, Hyung S. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S150000, C711S151000, C711S167000, C713S400000

Reexamination Certificate

active

07350051

ABSTRACT:
A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.

REFERENCES:
patent: 6209053 (2001-03-01), Kurts
patent: 7111153 (2006-09-01), Kuttanna et al.
Moore et al. (Translation Lookaside Buffer Cycle Stealing) (IBM Technical Disclosure Bulletin, vol. 37, No. 04B, Apr. 1994), pp. 527-528.

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