Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-05-20
2008-05-20
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C324S522000, C324S537000, C702S065000, C702S066000
Reexamination Certificate
active
11398980
ABSTRACT:
An example method of monitoring and measuring the line width of interconnects comprising the following steps. First, we measure an I-V profile of a sample interconnect structure to obtain a sample I-V profile. The I-V profile is comprised of leakage current measurements at two or more voltages. The sample interconnect structure is comprised of spaced lines having a line spacing. Next we compare the sample I-V profile with a reference I-V profile at a reference line spacing to determine if sample interconnect structure is not defective. If the sample I-V profile is similar to the reference I-V profile, then leakage currents for the sample interconnect structure are derived from the I-V profiles at a selected voltages. Then we calculate the line spacing of the sample interconnect structure using the sample I-V profile.
REFERENCES:
patent: 6242757 (2001-06-01), Tzeng
patent: 6573498 (2003-06-01), Rangarajan et al.
patent: 6754593 (2004-06-01), Stewart et al.
patent: 6891627 (2005-05-01), Levy
patent: 2002/0102472 (2002-08-01), Chan
patent: 2002/0107650 (2002-08-01), Wack et al.
patent: 2003/0155933 (2003-08-01), Wang
patent: 2005/0017171 (2005-01-01), Samuelson et al.
patent: 2005/0266652 (2005-12-01), Chudzik et al.
Jason P. Cain and Costas J. Spanos, Electrical linewidth metrology for systematic CD variation characterization and causal analysis, found Jul. 18, 2005 on website (see below).
http://www.eecs.berkeley.edu/˜neureuth/FLCC/papers/spie—mi—5038-35.pdf , 12 pages, Department of Electrical Engineering and Computer Sciences, University of California.
Chung Ching Thiam
Qian Hua
Chartered Semiconductor Manufacturing Ltd.
Horizon IP Pte Ltd
Kik Phallaka
Lin Aric
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