Method to manufacture high voltage MOS transistor by ion...

Details Method to manufacture high voltage MOS transistor by ion... Method to manufacture high voltage MOS transistor by ion...

2006-04-04

2006-04-04

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S194000, C438S197000, C438S282000, C438S289000

Reexamination Certificate

active

07022560

ABSTRACT:
A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain region (45), and a channel region (31), the channel having a short length and becoming well aligned with the gate edge. The deep n-well (11) and the p-well (19) are both produced by ion implantation. The method is compatible with a standard CMOS process and gives low manufacturing costs, increased breakdown voltage, better overall high-frequency performance, and the prevention of the “body effect” occurring by isolation of the p-well.

REFERENCES:
patent: 5146298 (1992-09-01), Eklund
patent: 5286995 (1994-02-01), Malhi
patent: 5854099 (1998-12-01), Farrenkopf
patent: 5985705 (1999-11-01), Seliskar
patent: 6069034 (2000-05-01), Gregory
patent: 6225181 (2001-05-01), Gregory

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