Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-05-24
2000-04-11
Fahmy, Wael
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438428, 438438, H01L 2176
Patent
active
060487755
ABSTRACT:
A method of planarizing a non-conformal HPDCVD STI oxide isolation using an underlying first nitride layer and an overlying second nitride polish stop layer. The HPDCVD oxide is deposited so that the second nitride polish stop is formed coplanar with the first nitride layer over the center of narrow trenches. Both first and second nitride layers act as polish stops. The invention forms a first nitride layer over the substrate. Wide and narrow trenches are then etched in the substrate. In an important step, a non-conformal HDPCVD oxide layer is formed filling the trenches to a level about 500 .ANG. above the substrate surface. Then a second nitride layer is formed over the non-conformal HDPCVD oxide layer. Next, the structure is chemical-mechanical polished using both the first and nitride layers as polish stops. The second nitride layer and narrow extruded parts of the HDP-CVD oxide layer are removed in a DHF etch. Next, the first nitride layer is removed.
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Chang Randy
Hsu Stanley
Lin Albert
Yao Liang-Gi
Ackerman Stephen B.
Fahmy Wael
Pham Long
Saile George O.
Stoffel William J.
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