Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2003-07-29
2004-07-27
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S234000, C438S236000, C438S294000, C438S335000, C438S514000, C438S519000, C438S526000
Reexamination Certificate
active
06767810
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to structure and fabrication methods of MOS transistors, which have an increased substrate potential for improved ESD protection.
DESCRIPTION OF THE RELATED ART
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (“Human Body Model”, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (“machine model”, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the “charged device model” (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, “ESD in Silicon Integrated Circuits” (John Wiley & Sons LTD. London 1995), and C. Duvvury, “ESD: Design for IC Chip Quality and Reliability” (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields—all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak NMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Such substrate biasing can be effective at improving the response of a multi-finger MOS transistor that is used to conduct an ESD discharge to ground. However, substrate biasing can cause the threshold voltages for devices to change from their nominal values, which may affect device operation. In addition, substrate biasing under steady-state conditions causes heat generation and increases power losses.
Solutions offered in known technology require additional IC elements, silicon real estate, and/or process steps (especially photomask alignment steps). Their fabrication is, therefore, expensive. Examples of device structures and methods are described in U.S. Pat. No. 5,539,233, issued Jul. 23, 1996 (Amerasekera et al., “Controlled Low Collector Breakdown Voltage Vertical Transistor for ESD Protection Circuits”); U.S. Pat. No. 5,793,083, issued Aug. 11, 1998 (Amerasekera et al., “Method for Designing Shallow Junction, Salicided NMOS Transistors with Decreased Electrostatic Discharge Sensitivity”); U.S. Pat. No. 5,940,258, issued Aug. 17, 1999 (Duvvury, “Semiconductor ESD Protection Circuit”); U.S. Pat. No. 6,137,144, issued Sep. 24, 2000, and U.S. Pat. No. 6,143,594, issued Nov. 7, 2000 (Tsao et al, “On-Chip ESD Protection in Dual Voltage CMOS); and U.S. patent application Ser. No. 09/456,036, filed Dec. 3, 1999 (Amerasekera et al., “Electrostatic Discharge Device and Method”).
With the continued scaling in deep submicron technologies, it is important to search for ways to increase the strength of bipolar turn-on of nMOS transistors used in ESD protection circuits based on snap-back characteristics. In addition, the challenge of cost reduction implies a drive for minimizing the number of process steps, especially a minimum number of photomask steps, and the application of standardized process conditions wherever possible. These constraints should be kept in mind when additional process steps or new process conditions are proposed to improve ESD insensitivity without sacrificing any desirable device characteristics. An urgent need has, therefore, arisen for a coherent, low-cost method of enhancing ESD insensitivity without the need for additional, real-estate consuming protection devices. The device structure should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
The present invention describes an integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity; the region extends between the isolation trenches. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad. The space may have a linear or meandering outline.
In the first embodiment of the invention, the space between the contact and the source includes a dummy gate. In the second embodiment, the space includes an isolation region. In the third embodiment, the space includes a protected, stable surface. In all embodiments, the region of higher resistivity may have a resistivity about an order of magnitude higher than the first resistivity, and this higher resistivity is brought about by a compensating doping process according to the invention.
The dummy gate structures of the first embodiment are formed concurrently with the MOS gate structures. Consequently, the distribution of the subsequently implanted ions is modulated so that the junction between the second well and the region of higher resistivity of the first well has variable distance to the chip surface in accordance with the configuration of the transistor gate and dummy gate structures.
The isolation region in the space between contact and source of the second embodiment is formed before second-well ion implant. Consequently, the second well has to be created by ions implanted with higher energy than in the first embodiment and the junction between the second well and the region
Chatterjee Amitava
Kim Young-min
Salling Craig T.
Hogans David L.
Nguyen Tuan H.
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