Method to improve TiSix salicide formation

Details Method to improve TiSix salicide formation Method to improve TiSix salicide formation

2000-01-18

2001-09-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S682000

Reexamination Certificate

active

06294448

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to improve TiSi
x
salicide formation by adding an extra As or BF
2
implant after Resist Protection Oxide (RPO) etching.
(2) Description of the Prior Art
The category of semiconductor devices that is commonly referred to as Field Effect Devices (FET's) forms an important class of devices that has, as a consequence, received a considerable amount of attention in its construction and the many refinements that have been applied to this construction. The main thrust of the refinements that have been applied to these devices has been provided by the continued decrease in device size that has led to continued device improvements. In its simplest form, the FET consists of a gate electrode structure, typically formed of polysilicon, that is formed on the surface of a layer of gate oxide that has been deposited on the surface of a semiconductor substrate. Self-aligned with and adjacent to the gate electrode are two regions in the surface of the substrate of opposite conductivity type that are referred to as the source and the drain regions. Points of electrical contact are established to the source and drain regions in addition to the surface region of the gate electrode.
With the continued decrease in device dimensions, it has become increasingly more important to find solutions to problems that are caused by misalignments between the successive mask patterns that are applied to create FET devices. It is for instance of great importance that the source and drain regions are in good alignment with the gate electrode, it is also of great importance that regions to which electrical contacts are to be established are in good alignment in order to assure electrical isolation and the avoidance of electrical shorts between these regions. By using the body of the gate electrode as a mask during ion implantation for the creation of the source and drain regions, good alignment can be obtained for these regions. To separate the source/drain contacts from the contact that is established with the surface of the gate electrode, gate spacers are created on the sidewalls of the gate electrode. To further reduce contact resistance with the points of electrical contact of the gate electrode, these contact regions are salicided. This is accomplished by forming a silicide film of a metal that has a high melting point on these surfaces. A titanium silicide film is mainly used as the high melting point silicide film while cobalt silicide and nickel silicide film have also been investigated. The basic success of forming salicided contact layers can be achieved due to the fact that certain metals, such as titanium or cobalt, react when heated while they are in contact with silicon. This reaction forms conductive silicides over the surface of the silicon while the metal however does not react with silicon oxides. By forming silicon oxide spacers on the sidewalls of the gate electrode, the deposited metal does not interact with the sidewalls of the gate electrode and separate points of electrical contact can be formed for the source/drain regions and the surface of the gate electrode.
For the operation of a FET device, an electrical voltage is applied between the source and the drain regions. Very little current will flow as a result of this electrical voltage because one of the two interfaces (PN junctions) that exist between the underlying silicon substrate and the source/drain regions will always be back biased. The region of the silicon substrate that exists underneath the gate electrode can however be electrically controlled (biased) such that the minority carriers that are present in this region (the channel region) are increased to a level that is sufficiently high such that this region assumes the same conductivity type as the source/drain regions and, as a consequence, current can flow more freely. Improved FET device performance is achieved by reducing the channel length of the device while simultaneously keeping the resistance between the channel region and the source/drain regions as high as possible. The latter objective is accomplished by the introduction of Lightly Doped Drain (LDD) regions that extend from both sides of the gate electrode with a very light (and not deep) implant into the surface of the substrate.
The formation of an n-type channel MOS device that has salicided source/drain contacts in addition to salicided gate electrode will be detailed below.
FIG. 1
shows a cross section of a p-type semiconductor surface
10
, field isolation regions
11
of thick oxide have been provided in the surface of the substrate to define the active regions in the surface of the substrate. A thin layer
12
of gate oxide has been formed using methods of thermal oxidation, a layer
14
of polysilicon is deposited over the surface of the gate oxide layer
12
, this layer
14
of poly is provided with a n-type conductivity and patterned to form to body of the gate electrode. The etch that is required to form the body of the gate electrode removes the deposited layer of poly and the deposited layer of gate oxide in accordance with the pattern of the gate electrode. An n-type ion implant
18
is performed into the surface of the substrate, this implant is self-aligned with the body
14
of the gate electrode and forms the LDD regions of the gate electrode. The gate spacers
16
are next formed by a thermal deposition of a layer of silicon nitride over the surface of the gate electrode and its surrounding area, the layer
16
of silicon nitride is anisotropically etched back thereby forming the gate spacers
16
on the sidewalls of the gate electrode. A second, relatively deep and heavily doped n-type implant
20
/
21
is performed into the surface of the substrate
10
to form the source and drain regions
20
/
21
of the gate electrode
14
. The region
18
of the LDD region is now concentrated under the spacers
16
of the gate electrode. The next step in the process is the step of forming contacts with the gate electrode source (
20
) and drain (
21
) regions and the surface of the gate electrode
14
. A layer
24
of refractory metal is blanket deposited over the entire structure. The structure that is shown in
FIG. 1
is subjected to a heat treatment that causes layer
24
to react with the underlying layer
14
of poly and the underlying surface of the source and drain regions
20
and
21
whereby this layer of refractory metal
24
is fully converted to a silicide. The unreacted refractory metal has not formed silicide and is therefore removed by applying a selective etch that essentially removes the metal from the surface of the gate electrode spacers
16
leaving the silicided metal in place over the surface of the source
20
and drain
21
regions in addition to leaving the silicided metal in place over the surface of the gate electrode
14
. A cross section of the gate structure after the process of removing the unreacted refractory metal has been removed from the structure is shown in
FIG. 2
where the layers
24
form the points of electrical contact to the gate electrode and the source and drain regions of this gate electrode.
During present salicidation processing, the processing step of depositing the layer
24
of refractory metal is preceded by an silicon ion implant into the surface of the substrate
10
in order to improve the formation of the silicided layers
24
. The results that are achieved by the silicon ion implant depend on this implant being performed in regions that have previously been subjected to the LDD and source/region implants of either n-type or p-type impurities. Where these implants for the LDD or source/drain regions have even minor misalignments and where therefore the silicon surface has an impurity concentration that is not uniform (the silicon surface contains intrinsic silicon devoid of a uniform impurity profile), the silicon ion implant that precedes that deposition of the refractory met

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