Method to improve the capacity of data retention and...

Details Method to improve the capacity of data retention and... Method to improve the capacity of data retention and...

2000-03-13

2001-12-04

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S321000, C257S323000

Reexamination Certificate

active

06326660

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, to forming split-gate flash memories with improved data retention capacity and increased coupling ratio between the source and the floating gate of the memory cell.
(2) Description of the Related Art
The importance of data retention capacity and the coupling between the gate and the source of a memory cell has been well recognized since the advent of the one-transistor cell memory cell with one capacitor. over the years, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a split-gate structure. A conventional stack-gate type cell is shown in
FIG. 1
a
where, as is well known, tunnel oxide film (
20
), a floating gate (
30
), an interpoly insulating film (
40
) and a control gate (
50
) are sequentially stacked on a silicon substrate (
10
) between a drain region (
13
) and a source region (
15
) separated by channel region (
17
). Substrate (
10
) and channel region (
17
) are of a first conductivity type, and the first (
13
) and second (
15
) doped regions are of a second conductivity type that is opposite the first conductivity type.
One of the problems that is encountered in flash memories is the “over-erasure” of the memory cell contents during erasure operations. As seen in
FIG. 1
a,
the stacked-gate transistor is capable of injecting electrons from drain (
13
), based on a phenomenon known as the Fowler-Nordheim Tunneling Effect, through tunneling oxide layer (
20
) into floating gate (
30
). The threshold voltage of a stacked-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflect the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source (
15
) through tunneling oxide layer (
20
) and out of floating gate (
30
) of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the stacked-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate, (
50
). This phenomenon is known in the art as memory over-erasure.
To overcome the described memory over-erasure problem of stacked-gate type EEPROM devices, a split-gate EEPROM device is used as shown in
FIG. 1
b.
This memory device comprises floating-gate transistor which similarly includes control gate (
50
′), floating gate (
30
′) as in the case of the stacked-gate transistor of
FIG. 1
a.
However, floating gate (
30
′) here covers only a portion of the channel region, (
17
′), and the rest of the channel region, (
19
′), is directly controlled by control gate (
50
′). This split-gate-based memory cell is equivalent to a series connected floating-gate transistor (
17
′) and an enhanced isolation transistor (
19
′), as is schematically represented in
FIG. 1
b.
The principal advantage of such configuration is that isolation transistor (
19
′) is free from influence of the state of floating gate (
17
′) and remains in its off-state, even if floating-gate transistor (
17
′) is subjected to the phenomenon of over-erasure and therefore, is in a conductive state. The memory cell can thus maintain its correct state irrespective of the over-erasure problem.
However, the greatest drawback of such split-gate design is the fact that a reduced number of program/erase cycles are allowed. This reduction is due to the fact that floating gate (
30
′) of this split-gate memory cell configuration is only provided near the drain region (
13
′), which results in different mechanisms occurring for the programming and erasing operations of the device. That is, electron passage must be via a sequence of drain (
13
′) and through tunneling oxide layer (
20
′), and the resulting reduction of allowable program/erase cycles renders the device suitable only for those applications requiring a relatively few number of program/erase cycles during the entire life span of the device.
To program the transistor shown in
FIG. 1
b,
charge is transferred from substrate (
10
) through gate oxide (
20
′) and is stored on floating gate (
30
′) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” of “off.” “Reading” of the cell's state is accomplished by applying appropriate voltages to the cell source (
15
′) and drain (
13
′), and to control gate (
50
′), and then sensing the amount of charge on floating gate (
30
′). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling mentioned above. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of (F-N) tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate F-N tunneling.
The thicknesses of the various portions of the oxide layers on the split-gate side (between the control gate and the source) and the stacked-side (between the floating gate and the drain) of the memory cell of
FIG. 1
b
play an important role in determining such parameters as current consumption, coupling ratio and the memory erase-write speed. In prior art, various methods have been developed to address these parameters. For example, in U.S. Pat. No. 5,592,002, Kanamori teaches the forming of a memory device having reduced current consumption. In his approach, a first oxide film is formed on the n-type impurity diffusion layer i

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