Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-14
2002-11-19
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S383000, C257S384000
Reexamination Certificate
active
06483153
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high-density semiconductor devices, and in particular, to a method to improve LDD corner control during a local interconnect trench oxide etch.
BACKGROUND OF THE INVENTION
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semiconducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using local interconnects.
The local interconnect is typically a relatively low resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or a trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the density of the circuits increases there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
A problem arises in the formation of a local interconnect due to the relatively poor etch selectivity of the oxide dielectric material to the etch stop layer typically used to prevent overetching into a diffusion region. The overetching may lead to disconnection of the diffusion region at a field edge and result in a poor interconnection. This may best be understood by reference to
FIGS. 1-3
to illustrate the concern.
FIG. 1
depicts a cross-section of a semiconductor device arrangement during one step of a local interconnect formation process. A silicon substrate
110
has polycrystalline silicon (hereafter polysilicon) gates
112
and
114
formed thereon. The polysilicon gate
114
is actually formed on the field oxide
116
. A spacer
115
(such as an oxide spacer or nitride spacer) provides a shielding of the substrate
110
directly under the spacer
115
during implantation or diffusion of dopant substrate
110
.
A plurality of silicide regions
118
are formed through conventional silicide techniques, for example, in a self-aligned silicide (“salicide”) technique. The material comprising the silicide regions
118
may be selected from different materials, such as titanium silicide, cobalt silicide, tungsten silicide, etc. Silicide regions
118
provide a low resistance contact for the semiconductor devices.
The doped active region
120
is provided in the substrate
110
as defined by the doping. Typically, a heating step is performed to activate the dopants following the introduction of the dopants into the substrate
110
.
An etch stop layer
122
is conformally deposited over the semiconductor wafer. An exemplary material for the etch stop layer is silicon oxynitride (SiON or SiN) and a conventional method of deposition is plasma enhanced chemical vapor deposition (PECVD). A layer of dielectric material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS), is deposited over the etch stop layer
122
and planarized. The dielectric layer
124
is then covered with a photoresist mask
126
which is patterned and developed with the desired local interconnect opening that is to be etched in the dielectric layer
124
. In this example of
FIG. 1
, the opening in the photoresist layer
126
is positioned to provide a local interconnect opening in the dielectric layer
124
that will eventually connect the gate
114
of one device with the active region
120
of another device.
An etching step is then performed that etches through the dielectric layer
124
in accordance with the pattern in the photoresist layer
126
. It is desirable to stop this first etching step at the etch stop layer
122
. However, as depicted in
FIG. 2
, it is often difficult to precisely stop the etch at the etch stop layer
122
, especially at the edge of the field
116
. In this circumstance, the local interconnect opening
128
undesirably extends into the substrate
110
at area
130
. The unintended etching through the etch stop layer
122
allows the etchant to etch the silicide region
118
and the diffusion region
120
, creating the dip
130
into the substrate
110
.
As seen in
FIG. 3
, after the deposition of a liner (or “barrier layer”) that prevents diffusion of the conductive material into the other areas of the device, the local interconnect opening
128
is filled with a conductive material, such as tungsten
134
. However, there remains a disconnection of the diffusion region
120
at the edge of the field
116
, caused by the overetching through the etch-stop layer
122
during the etching of the dielectric layer
124
. This disconnection and the reduced contact of the conductive metal
134
to the silicide region
118
of the diffusion region
120
decreases the performance of the circuit, and in extreme circumstances, may cause circuit failure.
There is a need for an improved etch selectivity to prevent the weakness at the field edge and disconnection of the diffusion region during a local interconnect formation process.
SUMMARY OF THE INVENTION
The present invention relates to high-density semiconductor devices, and in particular, to a method to improve LDD comer control during a local interconnect trench oxide etch on a semiconductor device. The present invention achieves this result by providing a first etch stop layer over the gate and active regions in the substrate and further providing thereon a second etch stop layer made of polysilicon and having a different composition than that of the first etch stop layer. By forming a second etch stop layer of polysilicon the present invention improves the selectivity of the local interconnect trench oxide etch, thereby improving the ability of the first and second etch stop layers to stop the etch process at the critical interfaces. This is particularly important for the area around the top comers of the gates and the LDD region that are subjected to extended overetching and physical bombardment during the etching of the oxide trench.
The present invention provides for a method for forming a viable local interconnect scheme. The method of the present invention includes the step of forming a gate on a substrate having active regions. A first etch stop layer is formed over the gate and over an exposed portion of the active regions. A second etch stop layer of polysilicon is formed over the first etch stop layer, where the second etch stop layer has a different composition than the first etch stop layer. The method further includes forming an oxide layer over the second etch stop layer and forming a trench in the oxide layer that extends to at least the second etch stop layer. The method includes removing an exposed portion of the first and second etch stop layers, and forming a local interconnect within the trench. Advantageously, the method of the present invention includes the incorporation of a second etch stop layer of polysilicon in order to improve the selectivity of the etch stop layers during the etching of the oxide trench.
The present invention additionally provides a semiconductor device including a gate located on a substrate having active regions. The device includes a first etch stop layer located over the gate and over an exposed portion of the active regions, and a second etch stop layer o
Besser Paul
Hui Angela
Ngo Minh-Van
Advanced Micro Devices , Inc.
Hu Shouxiang
Loke Steven
LandOfFree
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