Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-09-12
1999-09-07
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518501, 36518528, 36518526, G11C 1604
Patent
active
059497173
ABSTRACT:
A method to erase data from a flash EEPROM cell while electrical charges trapped in the tunnel oxide of a flash EEPROM cell are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a first relatively high positive voltage pulse to the source of the flash EEPROM cell. Simultaneously a ground reference voltage is applied to the control gate and to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying a second relatively high positive voltage pulse to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate.
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Ho Ming-Chou
Lee Jian-Hsing
Peng Kuo-Reay
Yeh Juang-Ker
Ackerman Stephen B.
Knowles Billy J.
Le Thong
Nelms David
Saile George O.
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