Method to improve cache capacity of SOI and bulk

Details Method to improve cache capacity of SOI and bulk Method to improve cache capacity of SOI and bulk

2005-08-23

2005-08-23

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06934182

ABSTRACT:
Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

REFERENCES:
patent: 6424015 (2002-07-01), Ishibashi et al.
patent: 6528897 (2003-03-01), Kuwazawa
patent: 6654277 (2003-11-01), Hsu et al.
patent: 6791895 (2004-09-01), Higeta et al.

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