Method to improve buried contact resistance

Details Method to improve buried contact resistance Method to improve buried contact resistance

1996-03-22

1997-01-21

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257900, H01L 2976, H01L 2994, H01L 27088

Patent

active

055962157

ABSTRACT:
A process for fabricating MOSFET devices, using an optimized buried contact approach, for source and drain contacts, has been developed. This process is forgiving for non-optimized photolithographic alignments, which when used as masks for dry etching, can result in the creation of trenches or crevices in the device region, ultimately degrading the conductive path from the buried contact region, to a polysilicon contact structure. Films used to create the spacer sidewalls on polysilicon gate structures, also fill the unwanted trench or crevice. Therefore materials are chosen, that have electrical charge characteristics of gate fringing field effects, that will result in the creation of a more conductive accumulation layer, for the contact path.

REFERENCES:
patent: 4341009 (1982-07-01), Bartholomew et al.
patent: 5315150 (1994-05-01), Furuhata
patent: 5320972 (1994-06-01), Wylie
patent: 5381040 (1995-01-01), Sun et al.

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