Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2004-02-17
2004-11-09
Gurley, Lynne A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S639000, C438S644000, C438S654000, C438S666000, C438S669000, C438S671000, C438S685000, C438S687000, C438S688000, C438S720000, C438S734000, C438S742000
Reexamination Certificate
active
06815337
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a borderless contact for a metal line structure overlying and contacting an underlying metal via structure.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed the performance of semiconductor devices to be improved, while processing costs for semiconductor chips comprised with sub-micron features, has been reduced. The use of sub-micron features allow decreases in performance degrading, parasitic junction capacitances to be realized, while a greater number of smaller semiconductor chips can be obtained from a specific size starting semiconductor substrate, thus reducing the processing cost for a specific semiconductor chip. The smaller semiconductor chips still provide device densities equal to, or greater than, counterpart semiconductor chips, comprised with larger features.
In addition to the use of sub-micron features specific design options, such as the use of borderless metal contact and line structures, have been used to reduce the size of semiconductor chips, thus again reducing the fabrication cost for a specific semiconductor chip. The borderless design allows for a non-fully landed metal structure to overlay and contact an underlying conductive region such as an underlying metal via, or metal interconnect structure. The luxury of not having to completely land on the underlying conductive region reduces the area of the underlying conductive region provided for contact by a subsequent overlying metal structure, thus allowing reductions of semiconductor chip size to be achieved. However the use of borderless designs can present problems when defining, via dry etching procedures, the overlying metal structure, specifically when a portion of the underlying metal structure is exposed to the final cycle of the overlying metal structure definition procedure, either by design or by mis-alignment. The non-selective definition, or dry etching procedure can result in unwanted removal of exposed underlying metal, specifically during an over etch cycle used to insure complete removal of the metal used for the overlying metal line or structure.
This invention will describe a novel process sequence in which the chance of exposure of the underlying metal structure to the dry etch procedure used to define a borderlsss, overlying metal structure, via mis-alignment or via intentional design ground rules, is reduced. This is accomplished by increasing the horizontal dimensions of the overlying, partially defined metal structure via formation of insulator spacers on the sides of a partially defined overlying metal structure, prior to completion of the definition procedure. The additional length or width of the overlying, partially defined overlying metal structure, provided by the insulator spacers, can protect previously exposed portions of the underlying metal structure from over etch cycles applied during the definition of the overlying metal structure. Prior art such as Hsu, in U.S. Pat. No. 6,077,770, describes a process of forming a damascene type, borderless metal interconnect structure, however that prior art does not describe the novel procedure detailed in the present invention in which insulator spacers are formed on a partially defined metal structure, than used as an etch mask to finalize the definition of the borderless metal interconnect structure.
SUMMARY OF THE INVENTION
It is an object of this invention to define an overlying metal structure on an underlying metal structure, without exposing the underlying metal structure to a dry etch procedure used to define the overlying metal structure.
It is another object of this invention to use a photoresist shape as an etch mask to define a partially defined metal structure in an insulator layer and in a top portion of a metal layer.
It is still another object of this invention to form spacers on the sides of the partially defined metal structure.
It is still yet another object of this invention to complete the definition of the overlying metal structure using the hard mask, comprised of the insulator shape on the partially defined metal structure, and the spacers on the sides of the partially defined metal structure, as the defining mask for the final metal structure shape.
In accordance with the present invention a method of defining an overlying metal structure on an underlying metal structure, with a reduced risk of exposing the underlying metal structure to the overlying metal structure definition process, via mis-alignment or intentional design, is described. After definition of an damascene type, underlying metal structure formed in an interlevel, or intermetal dielectric layer, a metal layer and an overlying, thin insulator layer are deposited. A photoresist shape is used as a mask to allow a dry etch procedure to define a shape in the thin insulator layer, and in a top portion of the metal layer. After removal of the photoresist shape, insulator spacers are formed on the exposed sides of the partially defined metal shape. The partially defined metal shape, overlaid with the thin insulator layer, and comprised with insulator spacers, are then used as an etch mask to complete the definition of a metal structure, which overlays, and contacts the underlying metal structure.
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Ackerman Stephen B.
Episil Technologies Inc.
Gurley Lynne A.
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