Method to identify geometrically non-overlapping...

Details Method to identify geometrically non-overlapping... Method to identify geometrically non-overlapping...

2006-05-16

2006-05-16

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07047506

ABSTRACT:
A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.

REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 6415426 (2002-07-01), Chang et al.
patent: 6446239 (2002-09-01), Markosian et al.
patent: 6449761 (2002-09-01), Greidinger et al.
“Multi-objective circuit partitioning for cutsize and path-based delay minimization”, Ababei et al., 2002 IEEE, pp. 181-185.

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