Method to form trench-free buried contact in process with STI te

Details Method to form trench-free buried contact in process with STI te Method to form trench-free buried contact in process with STI te

1998-06-18

2000-07-25

Nelms, David

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

438238, 438357, H01L 2176

Patent

active

060936193

ABSTRACT:
A new method of forming a buried contact junction in a process involving shallow trench isolation is described. A first silicon oxide layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. An opening is etched in the first silicon nitride and pad oxide layers where they are not covered by a mask. The substrate underlying the opening is etched into to form a shallow trench. An oxide material is deposited over the surface of the first silicon nitride layer and within the shallow trench and planarized to the surface of the first silicon nitride layer wherein the oxide material forms a STI region. The first silicon nitride layer is removed whereby the STI protrudes above the pad oxide layer. The pad oxide layer is removed whereby the corners of the STI above the substrate are also removed. A second silicon nitride layer is deposited overlying a sacrificial oxide layer and etched away to leave silicon nitride spacers filling in and rounding the corners of the STI. The sacrificial oxide layer is removed. A gate electrode and source/drain regions are formed in and on the substrate wherein a source/drain is adjacent to the STI. The gate electrode and STI are covered with an insulating layer. An opening is etched through the insulating layer to the source/drain region wherein the silicon nitride spacer at the corner of the STI prevents etching of the STI. The opening is filled with a conducting layer to complete formation of a contact.

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Fazan et al. "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs", IEDM, 193, by IEEE, pp. 57-60.

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