Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2007-11-06
2007-11-06
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S633000, C438S637000, C438S687000, C438S704000, C438S740000, C438S745000
Reexamination Certificate
active
11298015
ABSTRACT:
In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.
REFERENCES:
patent: 5639697 (1997-06-01), Weling et al.
patent: 6486066 (2002-11-01), Cleeves et al.
U.S. Appl. No. 10/883,417, filed Jun. 30, 2004, Raghuram et al.
U.S. Appl. No. 11/097,496, filed Mar. 31, 2005, Chen et al.
Chen Yung-Tin
Dunton Samuel V
Angadi Maki
Norton Nadine
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