Method to form shallow trench isolations

Details Method to form shallow trench isolations Method to form shallow trench isolations

2000-10-06

2003-11-18

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000, C438S400000, C438S712000, C438S713000, C438S719000

Reexamination Certificate

active

06649486

ABSTRACT:

BACKGROUND OF THE INVENTION
1 Field of the Invention
The invention relates to a method of fabricating semiconductor devices, and more particularly, to the fabrication of shallow trench isolation structures in the manufacture of an integrated circuit device.
2 Description of the Prior Art
The use of shallow trench isolation (STI) for the formation of integrated circuit isolations has grown in the art due to the reduced surface area and improved topology of STI when compared to traditional local oxidation of silicon (LOCOS) schemes. However, as the space between active regions shrinks with advancing technology, it is becoming more challenging to form STI.
Referring to
FIG. 1
, a cross-section of a partially completed prior art integrated circuit is shown. In this first prior art example, trenches
22
and
24
are formed in a semiconductor substrate
10
. Prior to formation of the trenches, a pad oxide layer
14
is formed overlying the semiconductor substrate
10
. A silicon nitride layer
18
is deposited overlying the pad oxide layer
14
. The silicon nitride layer
18
and the pad oxide layer
14
are then patterned to expose the semiconductor substrate
10
where the trenches
22
and
24
are planned.
The trenches
22
and
24
are then etched using an anisotropic dry plasma etching process. In the first prior art example, the trench etch angle
31
is less than about
70
degrees. Note that this angle
31
is sufficient to form the wide trench
22
but is insufficient to form a flat bottom on the narrow trench
24
. The silicon nitride layer
18
has a low etching rate in this trench etch process. Therefore, the thickness of the silicon nitride layer
18
is reduced
30
by only a small amount during the etch process. Variation in the thickness of the silicon nitride layer
18
can cause variation in the thickness of the final STI isolation layer because the silicon nitride layer
18
is the polishing stop for the chemical mechanical polish (CMP) process.
Referring now to
FIG. 2
, a second example of a prior art STI is illustrated. In this example, the trench etch angle
32
is increased to between about 75 degrees and 83 degrees. Note that this etch angle
32
is sufficient to form a flat-bottomed narrow trench
24
. However, increasing the trench etching angle brings a disadvantage. By increasing the angle at which the ionic plasma strikes the wafer surface, the etch rate of the silicon nitride layer
18
is also increased. For example, as the trench etch angle increase from 77 degrees to 81 degrees, the silicon nitride layer
18
loss increases from about 300 Angstroms to about 700 Angstroms. The second prior art example therefore exhibits a much greater loss 33 of silicon nitride layer
18
due to the trench etching process. This loss of hard mask material
18
causes inconsistency and non-uniformity in the thickness of the final STI isolation layer. At a minimum, a thicker silicon nitride layer
18
must be deposited to insure that the large angle trench etching process does not punch through. However, increasing the silicon nitride layer
18
thickness also increases the tensile stress and the probability of stress-related device leakage.
Several prior art approaches disclose methods to form shallow trench isolation in the semiconductor substrate. U.S. Pat. No. 6,027,982 to Peidous et al teaches a method to form STI with improved isolation fill and surface planarity. After the trench etch, the silicon nitride masking layer is laterally undercut at the trench edges by etching to thereby expose the substrate surface near the trench edges. A liner oxide layer is then grown in the trenches and the exposed substrate surface. The thin oxide layer overlying the silicon nitride masking layer enables the selective lateral undercutting process. U.S. Pat. No. 6,040,231 to Wu discloses an STI process whereby a pad oxide layer is laterally undercut by etching. Salicide is then formed in the exposed substrate. The salicide is removed to create an a slope periphery on the trenches. U.S. Pat. No. 6,057,210 to Yang et al teaches a method to form STI using an indirect CMP process. After trench formation and filling, the trench filling oxide is etched down by a wet etch. A silicon nitride layer is deposited overlying the filling oxide and is then polished down to expose raised portions of the filling oxide. The exposed filling oxide is removed. The silicon nitride layer is removed to complete the STI.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate narrow trenches for shallow trench isolations by facilitating the use of a large trench etching angle process.
A further object of the present invention is to provide a method to use a large trench etching angle while avoiding silicon nitride masking layer loss.
Another further object of the present invention is to reduce variation in STI thickness due to silicon nitride layer loss during the trench etch process.
A yet further object of the present invention is to prevent silicon nitride masking layer loss through the use of an overlying protective layer.
Another yet further object of the present invention is to reduce silicon nitride masking layer loss due to high density plasma sputtering.
In accordance with the objects of this invention, a new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents etching of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.


REFERENCES:
patent: 6027982 (2000-02-01), Peidous et al.
patent: 6037237 (2000-03-01), Park et al.
patent: 6040231 (2000-03-01), Wu
patent: 6057210 (2000-05-01), Yang et al.
patent: 6080637 (2000-06-01), Huang et al.
patent: 6110797 (2000-08-01), Perry et al.
patent: 6140242 (2000-10-01), Oh et al.
patent: 6180490 (2001-01-01), Vassiliev et al.
patent: 6261914 (2001-07-01), Divakaruni et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6287974 (2001-09-01), Miller
Chang et al, ULSI Technology, McGraw-Hill, 1996, p. 215-217.

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