Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-03-21
2001-05-08
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C438S745000, C438S756000, C438S757000
Reexamination Certificate
active
06228770
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming self-sealing air gaps between metal interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Advances in integrated circuit manufacture have enabled the formation of very narrowly spaced metal interconnections. Such metal interconnect processes allow greater device density in the completed circuit. Unfortunately, as the line to line spacing in the interconnect layers is made smaller, the capacitive coupling between the lines becomes greater. Increased capacitive coupling causes cross-talk, where voltage fluctuations on one line induce voltage fluctuations on an adjacent line. Capacitive coupling also causes a reduction in switching speeds as the total capacitive line load increases. Both of these problems can adversely affect performance and yield.
Capacitive coupling increases inversely as the distance between the metal lines decreases. To counter this phenomenon, there are only two alternatives. First, the metal lines may be made thinner to reduce the effective coupling area between the lines. Unfortunately, this increases the resistance of the metal traces and reduces switching speed. The preferred method to reduce coupling is to reduce the dielectric constant (&kgr;) of the material between the metal lines.
In recent years, many low dielectric materials have been proposed in the art for use as interlevel dielectrics. From a dielectric constant perspective, one of the best materials is air. Air has a dielectric constant of slightly greater than 1.0. By comparison, silicon dioxide has a dielectric constant of about 4.0. The capacitive coupling between adjacent metal lines can therefore be significantly reduced by replacing the typical silicon dioxide-based interlevel dielectric with air.
Several prior art approaches disclose methods to form air gaps between metal interconnections in the manufacture of an integrated circuit device. U.S. Pat. No. 5,461,003 to Havemann et al discloses a process to form low dielectric constant air gaps between adjacent metal lines on an integrated circuit device. A disposable solid material, such as photoresist, is deposited overlying the metal lines and filling the gaps between these metal lines. The disposable solid material is etched down to below the top surfaces of the metal lines. A porous dielectric layer is deposited overlying the metal lines and the disposable solid material. The disposable solid material is etched away by an etching process that can penetrate the porous dielectric layer. Etching processes, such as oxygen plasma and liquid acetone, are disclosed. Once the disposable solid material is removed, low dielectric constant air gaps are left between adjacent metal lines. Alternative embodiments include a passivation layer overlying the metal lines and an oxide layer overlying only the tops of the metal lines. U.S. Pat. No. 5,792,706 to Michael et al teaches a process to form low dielectric constant air gaps between and above metal lines. After metal line formation, a dielectric layer is deposited overlying and filling gaps between the metal lines. Deep, narrow trenches are etched through the dielectric layer. A capping layer of silicon dioxide is deposited overlying the dielectric layer. The capping layer cannot fill the deep, narrow trenches and merely seals the trenches to thereby form permanent air voids. U.S. Pat. No. 5,814,555 to Bandyopadhyay et al discloses a process to form voids in the dielectric layer between adjacent metal lines. The chemical vapor deposition (CVD) process conditions used in the deposition of the dielectric layer are conducive to forming voids.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming metal interconnects in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to form metal interconnects with reduced interlevel dielectric capacitance.
A still further object of the present invention is to reduce interlevel dielectric capacitance by forming air gaps between adjacent metal interconnects.
A yet still further object of the present invention is to form air gaps between adjacent metal interconnects using a self-sealing technique.
In accordance with the objects of this invention, a new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate comprising all layers and devices underlying planned metal interconnects is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited overlying the metal interconnects. A gap filling oxide layer is deposited overlying the silicon nitride liner layer and filling gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the top surface of the silicon nitride liner layer. A silicon nitride thin layer is deposited overlying the gap filling oxide layer and the silicon nitride liner layer. The silicon nitride thin layer is patterned using a mask that is an oversized and reversed representation of the mask used to pattern the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide layer between the adjacent metal interconnects. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.
REFERENCES:
patent: 5413962 (1995-05-01), Lur et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5792706 (1998-08-01), Michael et al.
patent: 5814555 (1998-09-01), Bandyopadhyay et al.
Chhagan Vijai Kumar
Gerung Henry
Mukhopadhyay Madhusudan
Pradeep Yelehanka Ramachandramurthy
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Powell William
Saile George O.
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