Method to form dual damascene structures using a linear...

Details Method to form dual damascene structures using a linear... Method to form dual damascene structures using a linear...

1999-09-20

2002-05-21

Fabuuy Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S637000, C438S638000, C438S639000

Reexamination Certificate

active

06391761

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to a method to fabricate dual damascene structures in the manufacture of integrated circuits.
(2) Description of the Prior Art
The implementation of dual damascene structures is a recent development in the field of integrated circuit manufacture. The dual damascene process allows for the formation of conductive wiring with very fine line widths and spaces.
In a damascene process, wiring trenches are formed in an isolation layer. Next, a conductive material is deposited overlying the isolation layer and filling the trenches. Finally, a chemical mechanical polish (CMP) is performed to polish down the conductive material to the surface of the isolation layer. In this way, the conductive traces of metal are formed.
The dual damascene process extends this idea by forming both the metal traces and via plugs in one metal deposition. This is accomplished by forming both the via trenches and the trace trenches in the isolation layer before the metal deposition.
Referring to
FIG. 1
, a cross-section of a partially completed dual damascene structure is shown. A substrate layer
10
is depicted. The substrate layer
10
encompasses all underlying layers, devices, junctions, and other features that have been formed prior to the deposition and definition of the conductive traces
18
and the isolation layer
14
. An anti-diffusion layer
22
composed of silicon oxynitride overlies the conductive traces
18
and the isolation layer
14
. A via-level dielectric layer
26
composed of oxide overlies the anti-diffusion layer
22
. An etch stopping layer
30
of silicon oxynitride overlies the via-level dielectric layer
26
. An interconnect dielectric layer
34
of oxide overlies the etch stopping layer
30
.
A layer of photoresist
38
is applied overlying the interconnect dielectric layer
34
. The photoresist layer
38
is developed to create openings where vias will be formed. The vias will connect upper-level metal traces to the underlying conductive traces. After an etch process is performed using the photoresist as a mask, the via trenches are etched through the interconnect dielectric layer
34
, the etch stopping layer
30
, and the via-level dielectric layer
26
.
After the via trenches are etched, as shown in
FIG. 2
, the first layer of photoresist
38
is stripped away. Now, as is typical in the prior art, a second layer of photoresist
42
is applied and developed. The openings in the second photoresist
42
expose the areas where the upper level trench will be formed. In this particular dual damascene structure, a dense array of closely spaced vias has been formed. Only one upper level trench will be formed overlying these vias.
Using the second photoresist as a mask
42
, the metal level trench is now etched. The etch chemistry is specially selected such that the etch rate for the oxide of the interconnect dielectric layer
34
is greater than that for the silicon oxynitride etch stopping layer
30
. Once the interconnect dielectric layer
34
is etched through to expose the underlying etch stopping layer
30
, the etch is stopped. By design, the etch stopping layer
30
protects the via-level dielectric layer
26
from the etch, and thereby maintains the integrity of the via profiles.
However, as shown in
FIG. 3
, problems can arise in the prior art dual damascene technique. Because of the close spacing of the vias in the dense array, the oxide etch rate in the dense array area is increased. This causes an etch rate microloading between different via trenches. The effect is seen in faceting
46
of the via isolation profiles. If this problem occurs in the fabrication of the dual damascene structure, there is a high likelihood of metal to metal shorting across vias in the dense array area. Moreover, the dense via merge issue tends to induce a process difficulty in the following CMP process.
In an attempt to reduce the likelihood of this problem, the etch stopping layer
30
can be made thicker. If the etch stopping layer
30
is made thick enough, the faceting problem can be eliminated. However, this creates a new problem. Because the silicon oxynitride material of the etch stopping layer
30
has a relatively highdielectric constant, a thickening of the layer causes an increase in the line-to-line capacitance between the metal in the vias. This increase in capacitance loading represents a problem in higher speed applications.
Several prior art approaches attempt to form dual damascene structures. U.S. Pat. No. 5,840,625 to Feldner teaches a process to fabricate metal interconnects using tungsten and aluminum where tungsten or tungsten nitride is used to line either damascene or dual damascene trenches. U.S. Pat. No. 5,753,967 to Lin discloses a process to form damascene and dual damascene trenches where a vertical liner is formed to reduce the trench width. U.S. Pat. No. 5,767,582 to Lee et al shows a dual damascene process. U.S. Pat. No. 5,635,423 to Huang et al discloses a dual damascene process with an embodiment using a liner in the top trench.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits with dual damascene structures.
A further object of the present invention is to provide a method of fabricating dual damascene trenches using a liner layer to protect the via trenches during the etch of the metal level trenches.
A yet further object of the present invention is to provide a method of fabricating dual damascene metal interconnect and vias using a liner layer to protect the via trenches during the etch of the metal level trenches.
Yet another object of the present invention is to provide a method of fabricating dual damascene trenches in which the via top corner profile is improved.
Yet another object is to provide a method of fabricating dual damascene trenches in which rounding of the via top corners is prevented.
Yet another object is to provide a method of fabricating dual damascene trenches in which rounding of the via top corners is prevented by a liner layer within the via trenches.
A further object is to provide a method of fabricating dual damascene trenches using a liner layer to prevent rounding of the via top corners wherein the etch stop layer thickness can be decreased.
In accordance with the objects of this invention, a new method of fabricating an integrated circuit with dual damascene structures is achieved. A substrate layer is provided encompassing all underlying layers, devices, and junctions. Conductive plugs are provided in an isolating dielectric layer. An anti-diffusion layer is deposited overlying the conductive plugs and the isolating dielectric layer. A via-level dielectric layer is deposited overlying the anti-diffusion layer. An etch stopping layer is deposited overlying the via-level dielectric layer. An interconnect dielectric layer is deposited overlying the etch stopping layer. A first photoresist layer is applied overlying the interconnect dielectric layer. The first photoresist layer is developed to expose the underlying interconnect dielectric layer where via trenches overlying the conductive plugs are planned. The interconnect dielectric layer, etch stopping layer and via-level dielectric layer are etched through using the first photoresist layer as an etching mask to form the via trenches. The remaining first photoresist layer is stripped away. A liner layer is deposited overlying the interconnect dielectric layer and the internal surfaces of the via trenches. A barrier and anti-reflective coating layer is deposited overlying the liner layer. A second photoresist layer is applied overlying the barrier and anti-reflective coating layer. The second photoresist layer is developed to expose the underlying interconnect dielectric layer where metal interconnect trenches overlying at least a portion of the via trenches are planned. The exposed portion of the barrier and anti

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