Method to form copper interconnects by adding an aluminum...

Details Method to form copper interconnects by adding an aluminum... Method to form copper interconnects by adding an aluminum...

1999-09-03

2004-05-25

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S628000, C438S633000, C438S637000, C438S687000

Reexamination Certificate

active

06740580

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to a method to form copper interconnects using an aluminum layer as gettering agent in the copper diffusion barrier layer in the manufacture of integrated circuits.
(2) Description of the Prior Art
As integrated circuit feature sizes continue to decrease, it has become advantageous to construct metal connections out of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.
To use copper effectively in an integrated circuit technology, however, the problem of copper diffusion into other materials must be addressed. For example, copper diffuses into common dielectrics, such as silicon dioxide, much more easily than does aluminum. This phenomenon can cause electrical leakage paths and shorts in the completed circuit.
Referring to
FIG. 1
, a cross-section of a partially completed prior art copper interconnect structure is shown. Because copper is more difficult to reliably etch than aluminum, a damascene approach is typically used to form copper interconnects. A substrate layer
10
is depicted. The substrate layer
10
encompasses all underlying layers, devices, junctions, and other features that have been formed prior to the deposition and definition of metal traces (Cu, Al, W, etc.,)
18
in an isolation layer
14
. A dielectric layer
22
overlies the isolation layer
14
and the copper traces
18
.
Via openings are formed in the dielectric layer
22
to expose the top surfaces of the conductive traces
18
. The via openings are typically etched using a reactive ion etch and then cleaned. In the process of etching and cleaning the vias, however, copper from the copper traces
18
can contaminate the sidewalls
26
of the vias.
Referring now to
FIG. 2
, a barrier layer
30
is deposited overlying the dielectric layer
22
and the exposed conductive traces
18
. A copper layer will subsequently be deposited overlying the barrier layer
30
to fill the vias. The purpose of the barrier layer
30
is to prevent copper out diffusion into the dielectric layer
22
while establishing a low resistance contact path to the underlying copper traces
18
. This barrier layer
30
is commonly comprised of tantalum, tantalum nitride or both tantalum and tantalum nitride.
The use of tantalum and tantalum nitride for the diffusion barrier creates two problems however. First, while the tantalum enhances the field adhesion for the copper layer, the chemical inertness and mechanical hardness of tantalum makes this barrier layer difficult to planarize in later process steps. Second, the tantalum and tantalum nitride barrier layer
30
cannot act as a copper plating catalyst. Therefore, a copper seed layer has to be deposited for subsequent copper plating by either electrochemical copper plating or electroless copper plating.
Unfortunately, the commonly used technology for depositing the tantalum, tantalum nitride, and copper seed layer is physical vapor deposition (PVD). The PVD technology provides relatively poor step coverage. Therefore, a substantial minimum thickness of barrier layer
30
is required. When coupled with the requirement of the additional copper seed layer, the process of the prior art is not extendible to the very small feature sizes of the future technology.
Several prior art approaches attempt to improve the barrier layer in copper interconnect processes for use in integrated circuit metalization. U.S. Pat. No. 5,695,810 to Dubin et al discloses a process to form a barrier layer composed of cobalt tungsten phosphide (CoWP) for copper interconnects. The prior art section also discusses barrier layers of Ta, Mo, W, TiW, TiN, WN, TiSiN, Ni, Co, and Ni—Co alloys. U.S. Pat. No. 5,801,100 to Lee et al teaches the use of a nickel containing layer as a copper diffusion barrier in an interconnect process. U.S. Pat. No. 5,821,168 to Jain discloses a process to form copper structures where an insulating layer is nitrided to form a barrier layer. An adhesion layer of silicon, silicon germanium, germanium, magnesium, or titanium is then deposited before the electroplating of copper. U.S. Pat. No. 5,674,787 to Zhao et al teaches a process to selectively deposit copper to form interconnects. Barrier layers of TiN, TiW, Ta, TaN, and WN are disclosed.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits with copper interconnects.
A further object of the present invention is to provide a method of fabricating copper interconnects with a diffusion barrier partially comprising aluminum.
A yet further object of the present invention is to form an improved barrier layer comprising aluminum and a second barrier material where the improved barrier layer further inhibits copper diffusion.
Another yet further object of the present invention is to form an improved barrier layer comprising aluminum and a second barrier material where the improved barrier layer has a much lower resistance.
Another further object of the present invention is to form an improved barrier layer comprising aluminum and a second barrier material where the second barrier layer provides a catalyst layer for seedless electrochemical or electroless copper plating.
In accordance with the objects of this invention, a new method of fabricating an integrated circuit with copper interconnects is achieved. A substrate layer is provided encompassing all underlying layers, devices, and junctions. Metal traces—Cu, Al, W, etc., are provided in a first dielectric layer. A second dielectric layer is deposited overlying the metal traces and the first dielectric layer. The second dielectric layer is patterned to form interconnect trenches for single or dual damascene interconnect structures. An aluminum barrier layer is deposited overlying the second dielectric layer and the exposed metal traces. A second barrier layer is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, second barrier layer, and aluminum barrier layer are polished down to the top surface of the second dielectric layer to define copper interconnects. An encapsulation layer is deposited overlying the copper interconnects and the second dielectric layer. A passivation layer is deposited overlying the encapsulation layer to complete the fabrication of the integrated circuit device.
In addition, in accordance with the objects of this invention, a new method of fabricating an integrated circuit with copper interconnects is achieved. A substrate layer is provided encompassing all underlying layers, devices, and junctions. Metal traces—Cu, Al, W, etc., are provided in a first dielectric layer. A second dielectric layer is deposited overlying the metal traces and the first dielectric layer. The second dielectric layer is patterned to form interconnect trenches for single or dual damascene interconnect structures. A titanium adhesion layer is deposited overlying the second dielectric layer and the exposed metal traces. An aluminum barrier layer is deposited by a high temperature process overlying the titanium adhesion layer. A second barrier layer is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, second barrier layer, aluminum barrier layer and titanium adhesion layer are polished down to the top surface of the second dielectric layer to define copper interconnects. An encapsulation layer is deposited overlying the copper interconnects and the second dielectric layer. A passivation layer is deposited overlying the encapsulation layer to complete the fabrication of the integrated circuit device.


REFERENCES:
patent: 5164332 (1992-11-01), Kumar
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1

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