Method to form a via

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S640000, C257SE21496

Reexamination Certificate

active

07932175

ABSTRACT:
A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

REFERENCES:
patent: 5998292 (1999-12-01), Black et al.
patent: 6908856 (2005-06-01), Beyne et al.
patent: 2006/0046432 (2006-03-01), Sankarapillai et al.
patent: 2007/0048994 (2007-03-01), Tuttle
patent: 2008/0050911 (2008-02-01), Borthakur
Sparks, Terry G. and Jones, Robert E.; “Conductive VIA Formation Utilizing Electroplating”; filed Feb. 27, 2007; U.S. Appl. No. 11/679,512; 17 pages.
Ruythooren, W. et al.; “Via technology for 3D wafer stacking”; IMEC, Belgium 2006; 31 pages.

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