Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-01-24
2001-03-13
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S299000, C438S515000, C438S516000, C438S528000, C438S529000, C438S532000
Reexamination Certificate
active
06200887
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a smooth gate polysilicon sidewall in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, photolithography and etching are used to form structures such as polysilicon gates, local oxidation of silicon (LOCOS), shallow trench isolation (STI), and the like. The photoresist material is coated over the layer or layers to be etched. The photoresist is exposed to actinic light through a mask, then developed to form the photoresist mask for etching the underlying layer or layers.
Polysilicon is used as the gate electrode of MOS transistors. The gate electrode is fabricated by reactive ion etching of the polysilicon with the pattern defined by the photoresist mask. Using the current art, the sidewall of the polysilicon after etching is rough. The roughness is determined by the grain size of the polysilicon crystals at the time of etching. For ultrasmall geometry devices the grain size becomes comparable to the device line widths. This may lead to poor polysilicon critical dimension (CD) distribution after etch which in turn affects the control of parameters such as threshold voltage (V
t
) and drain saturation current (I
dsat
). Use of amorphous silicon for the gate material instead of polysilicon results in smoother sidewalls due to the absence of grains. This solution, however, results in an increase in undesirable polysilicon depletion effects causing higher gate oxide capacitance and higher threshold voltage.
U.S. Pat. No. 5,393,682 to Liu teaches a method of damaging a polysilicon layer, then using an anisotropic etch to more quickly remove the damaged layer. The result is a tapered, trapezoidal shaped gate structure rather than a rectangular gate. U.S. Pat. No. 5,731,239 to Wong et al teaches a method using a pre-amorphizing implantation resulting in smaller grain sizes. U.S. Pat. No. 5,548,132 to Batra et al teaches a method using an amorphizing silicon implant affecting grain sizes in polysilicon. U.S. Pat. No. 5,652,156 to Laio et al teaches a method of forming the gate using multiple layers of polysilicon and amorphized silicon.
SUMMARY OF INVENTION
Accordingly, it is the primary object of the invention to provide an effective and very manufacturable process for forming gate structures with minimal gate depletion effects.
It is a further object of the invention to form gate structures with smooth sidewalls.
It is a further object of the invention to form structures having feature sizes on the order of between 0.5 to 0.006 microns.
Another object of the invention is to improve critical dimension control in the gates of smaller devices.
Yet another object is to provide a method of amorphizing the gate structure sidewalls.
In accordance with the objects of the invention, a new method for forming a gate electrode with a smooth sidewall is achieved. A gate silicon oxide layer is provided on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon or polysilicon germanium of thickness from 800 to 5000 Angstroms is deposited overlying the gate silicon oxide layer. A masking oxide layer is deposited overlying the gate electrode layer. The masking layer is covered with a layer of photoresist. The photoresist is patterned using a photolithography process to provide a photoresist mask for the formation of the gate electrode. The photoresist mask and the masking oxide layer are etched vertically forming a mask for the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not covered by the masking oxide mask and, because of lateral scattering of the implant, also amorphizes a portion of the polysilicon area under the edge of the masking oxide layer. Thereafter, the amorphized silicon is removed by a conventional anisotropic dry etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask in the manufacture of an integrated circuit.
REFERENCES:
patent: 5236856 (1993-08-01), Chan et al.
patent: 5273924 (1993-12-01), Chan et al.
patent: 5393682 (1995-02-01), Liu
patent: 5548132 (1996-08-01), Batra et al.
patent: 5652156 (1997-07-01), Liao et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5879975 (1999-03-01), Karlsson et al.
Balasubramaniam Palanivel
Balasubramanian Narayanan
Kantimahanti Arjun
Pradeep Yelehanka Ramachandramurthy
Chartered Semiconductor Manufacturing Ltd
Pham Long
Pike Rosemary L. S.
Saile George O.
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