Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-01-19
2002-04-30
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000, C438S697000, C438S699000, C438S700000, C438S701000
Reexamination Certificate
active
06380088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to semiconductor devices and to an improved MOS transistor and the method of making an MOS transistor. More particularly, the present invention relates to a method to form a recessed source drain on a trench sidewall with a replacement gate technique.
2. Description of Prior Art
MOS transistors are well known in the art, however there are some structures of MOS transistors that show problems. High junction capacitance degrades speed and performance of a transistor. This high junction capacitance can be reduced by the sitting source drain on top of the shallow trench isolation of a transistor. High junction leakages produce size problems so that the transistor has to be made bigger then ideal. This high junction leakage can be reduced when only the lightly doped drain is on top of a substrate. Finally, scaling of the active area effects the overall package density of a transistor and a vertical active contact, results in a better smaller package of a transistor.
For Example, U.S. Pat. No. 5,795,811 (Kim et al.) discloses a shallow trench isolation process, but does not disclose the source drain sitting on top of the shallow trench isolation. U.S. Pat. No. 5,380,671 (Lur et al.) shows a buried contact method near the shallow trench isolations. U.S. Pat. No. 5, 643,822 (Furukawa et al.) teaches an ion implant into the shallow trench isolations silicon trench sidewalls. U.S. Pat. No. 5,879,998 (Krivokapic) shows a replacement gate process.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an improved MOS transistor and method of making an improved MOS transistor. Another purpose of the present invention is to provide an MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. MOS transistors are well known in the art, and it is well known in the art that they can be either an N-MOS transistor or a P-MOS transistor. In this application we will show an N-MOS transistor, but as well known in the art, one can easily apply these descriptions to a P-MOS transistor.
A method for forming an MOS transistor by first providing a substrate and forming a pad oxide over the substrate. Then forming an etch stop layer over the pad oxide and creating shallow trench isolations in the substrate pad oxide, and etch stop layers. Active areas of the substrate are located between the shallow trench isolations. Next holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions.
The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.
REFERENCES:
patent: 5380671 (1995-01-01), Lur et al.
patent: 5455189 (1995-10-01), Grubisich
patent: 5643822 (1997-07-01), Furukawa et al.
patent: 5710076 (1998-01-01), Dai et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5834360 (1998-11-01), Tesauro et al.
patent: 5879998 (1999-03-01), Krivokapic
patent: 6214670 (2001-04-01), Shih et al.
patent: 6225659 (2001-05-01), Liu
Chan Lap
Lee James Yong Meng
Leung Ying Keung
Pan Yang
Pradeep Yelehanka Ramachandramurthy
Chartered Semiconductor Manufacturing Inc.
Pike Rosemary L. S.
Saile George O.
Stoffel William J.
Tran Binh X
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