Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-05-02
2002-06-11
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S694000, C438S696000, C438S700000, C438S704000
Reexamination Certificate
active
06403485
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a transistor having raised source/drain regions and low parasitic capacitance in the manufacture of integrated circuits.
(2) Description of the Prior Art
Current methods of reducing source/drain capacitance typically involve forming source/drain regions over silicon-on-insulator (SOI) areas. However, SOI devices often suffer from floating body effects, which are difficult to overcome. It is desired to provide a method for forming a pseudo-SOI device which has the advantages of SOI for the source/drain regions, but which eliminates the floating body effects.
U.S. Pat. No. 5,683,924 to Chan et al teaches a method of forming elevated source/drain regions. However, this method relies on the elevation of field oxide isolation regions to define the boundaries of the polysilicon over the source/drain regions. It would be difficult to use the raised source/drain regions to also form local interconnect in this method. U.S. Pat. No. 5,275,960 to Yamaguchi et al teaches forming a a raised polysilicon source/drain region followed by formation of a T-shaped gate. U.S. Pat. No. 5,827,768 to Lin et al discloses the formation of raised source/drain regions where patterning of the polysilicon layer is performed before CMP. The S/D regions are formed by diffusion rather than by implantation. Salicidation is not possible in this method. U.S. Pat. No. 6,015,740 to Milic-Strkalj teaches a method of forming raised source/drain regions. U.S. Pat. No. 6,001,697 to Chang et al discloses a raised source/drain process. The polysilicon layer is not planarized. U.S. Pat. No. 5,843,826 to Hong shows a raised source/drain method using selective epitaxy and forming a transistor on top of the selective epitaxy.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming a pseudo-SOI CMOS device in the fabrication of an integrated circuit.
Another object of the present invention is to provide a method of forming a pseudo-SOI device where source/drain regions are formed on an insulator, but the transistor is formed on silicon in the fabrication of an integrated circuit.
Yet another object of the present invention is to provide a method of forming a pseudo-SOI CMOS device wherein source/drain regions can be extended for use as local interconnect.
A further object of the invention is to provide a method of forming a transistor having elevated source/drain regions that can be extended for use as local interconnect.
A still further object of the invention is to provide a method of forming a pseudo-SOI device where elevated source/drain regions are formed on an insulator, but the transistor is formed on silicon wherein the source/drain regions can be extended for use as local interconnect.
Yet another object of the present invention is to provide a method of forming a low parasitic capacitance pseudo-SOI device where elevated source/drain regions are formed on an insulator, but the transistor is formed on silicon wherein the source/drain regions can be extended for use as local interconnect.
In accordance with the objects of this invention the method of forming a pseudo-SOI device having elevated source/drain regions that can be extended for use as local interconnect is achieved. Shallow trench isolation regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated source/drain extensions are fabricated in and on the semiconductor substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the semiconductor substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the shallow trench isolation regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the shallow trench isolation region separating those active areas. Alternatively, the source/drain regions can be extended over the shallow trench isolation regions where a contact can be made. The hard mask layer is removed. Ions are implanted and driven in to form elevated source/drain regions within polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated source/drain regions in the fabrication of an integrated circuit.
REFERENCES:
patent: 5275960 (1994-01-01), Yamaguchi et al.
patent: 5683924 (1997-11-01), Chan et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5827768 (1998-10-01), Lin et al.
patent: 5843826 (1998-12-01), Hong
patent: 6001697 (1999-12-01), Chang et al.
patent: 6015740 (2000-01-01), Milic-Strkalj
patent: 6093628 (2000-07-01), Lim et al.
patent: 6143613 (2000-11-01), Lin
patent: 6171910 (2001-01-01), Hobbs et al.
patent: 6239472 (2001-05-01), Shenoy
Chan Lap
Keung Ying
Meng James Lee Yong
Pan Yang
Pradeep Yelehanka Ramachandramurthy
Chartered Semiconductor Manufacturing Ltd
Pike Rosemary L. S.
Saile George O.
Tran Binh X.
Utech Benjamin L.
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