Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-12-07
2003-12-09
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S386000, C438S735000
Reexamination Certificate
active
06660611
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabrication of a corrugated structure having enhanced capacitance characteristics. More specifically, the present invention relates to a method of forming a corrugated capacitor cell comprising multiple layers of alternating material having differing etch rates, hereby facilitating formation of rippled or corrugated capacitor walls for capacitor cells of semiconductor memory devices.
2. State of the Art
Dynamic random access memory, otherwise known as a DRAM memory chip, die, or device, is a popular type of semiconductor memory device. A DRAM memory device is essentially multiple arrays formed by a series of memory cells including a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET) and an associated capacitor connected thereto fabricated on a substrate, such as a silicon substrate. The memory cells are combined with peripheral circuits to form the DRAM device. The state of the memory cell, either charged or uncharged, represents the state of a binary storage element, zero or one, (data) stored by the DRAM device in the memory cell. Multiple capacitors on a single silicon substrate or chip are therefore capable of storing large amounts of data. The greater the number of capacitors formed on a substrate or chip, the greater the memory capabilities of the DRAM memory device.
The popularity of the DRAM memory device is a direct result of the low cost involved in the production and manufacture of large quantities of DRAM memory devices. However, as the demand for smaller semiconductor substrates or chips with larger storage capacities has evolved, the ability to produce DRAM memory devices meeting the new technological requirements becomes increasingly difficult. This is particularly evident as the size of the capacitor cell becomes increasingly smaller. As the capacitor cell size of a DRAM memory device decreases in size, the area of the memory substrate or chip allocated for the capacitor cell decreases in size, making it more difficult for the capacitor cell to store the required electrical charge for the desired period in the capacitor cell during operation of the DRAM memory device. It is necessary to address the demands for greater capacitor cell storage for DRAM memory devices which are ever decreasing in size.
One solution which is capable of providing the necessary number of capacitors on a DRAM memory device is the formation of stacked-type or trench-type capacitor cells having larger surface areas. Typical manners which may be used for increasing capacitor cell surface area for stacked-type capacitor cells are to use either fin-type capacitor cells, pillar-type capacitor cells, striated capacitor cell walls, rippled capacitor cell walls, or roughened-surface-type capacitor cell walls. Such types of stacked capacitor cells are described in U.S. Pat. Nos. 5,061,650, 5,240,871, 5,300,801, 5,466,627, 5,519,238, 5,623,243, 5,637,523, 5,656,536, 5,827,783, 5,843,822, and 5,879,987. It is further known to selectively texturize polysilicon electrodes with respect to neighboring dielectric surfaces in DRAM memory devices, such as described in U.S. Pat. No. 5,830,793.
However, construction of such capacitors having an increased surface area capacitor cell wall or electrode typically requires a restructuring of the process flow to facilitate manufacture of the capacitor cells. Further, the types of materials used for such capacitors having an increased surface area may require additional time for deposition or be difficult to deposit in a uniform manner using conventional deposition apparatus.
What is needed is a simple process for the construction of capacitor cells having increased wall area using existing equipment and processes so that existing process flow does not need to be altered or slowed down for the deposition process.
BRIEF SUMMARY OF THE INVENTION
The present invention comprises a method of forming a rippled or corrugated capacitor cell wall having increased surface area used in capacitors in DRAM memory chips and semiconductor devices. More specifically, the invention relates to a method of forming a rippled or corrugated capacitor cell wall having increased surface area in a DRAM memory device using alternating layers of silicate glass which are subsequently etched to form the corrugated cell wall structure. The corrugated capacitor cell is constructed of alternating layers of germanium boro-phospho silicate glass (Ge-BPSG) and boro-phospho silicate glass (BPSG) or nitro silicate glass (NSG) and etched to form the rippled or corrugated cell wall. The formation of corrugated wall capacitor cells using the methods disclosed herein may be accomplished using current semiconductor device process technologies for materials having deposition rates comparable to those of the materials normally used for deposition in such process technologies.
Alternating layers of Ge-BPSG and BPSG, or NSG, are deposited on electrical contacts of a DRAM memory device or metal oxide semiconductor field effect transistor (MOSFET) using chemical vapor deposition (CVD) processes or plasma enhanced chemical vapor deposition processes (PECVD) using suitable apparatus operating at either atmospheric pressure levels or sub-atmospheric pressure levels. The layers are deposited in clusters such that individual capacitance cells are formed having trenches or spaces between each capacitance cell. Once the desired capacitance cell thickness is reached, the capacitance cells are capped with an etch-resistant layer. Introduction of either a wet or dry etchant into the trenches between the capacitance cells, however, etches the alternating layers at varying rates, thereby forming the rippled or corrugated wall of each capacitor cell. The form of the rippled or corrugated configuration of the capacitor cell wall is dependent upon the etch rates of the alternating layers, and specifically on the concentration of germanium (Ge) in the Ge-BPSG layers forming the capacitor cell.
REFERENCES:
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5240871 (1993-08-01), Doan et al.
patent: 5300801 (1994-04-01), Blalock et al.
patent: 5466627 (1995-11-01), Lur et al.
patent: 5637523 (1997-06-01), Fazan et al.
patent: 5656536 (1997-08-01), Wu
patent: 5804506 (1998-09-01), Haller et al.
patent: 5827783 (1998-10-01), Hsia et al.
patent: 5843822 (1998-12-01), Hsia et al.
patent: 5879987 (1999-03-01), Wang
patent: 5889696 (1999-03-01), Kawakubo et al.
patent: 5930106 (1999-07-01), DeBoer et al.
patent: 5972769 (1999-10-01), Tsu et al.
patent: 6025225 (2000-02-01), Forbes et al.
patent: 6027970 (2000-02-01), Sharan et al.
patent: 6028763 (2000-02-01), Howard
patent: 6060355 (2000-05-01), Batra et al.
patent: 6074926 (2000-06-01), Cathey et al.
patent: 6124607 (2000-09-01), Sandhu et al.
patent: 6346455 (2002-02-01), Thakur et al.
patent: 6376303 (2002-04-01), Seo et al.
Wolf et al., “Silicon Processing for the VLSI Era”, vol. 1—Process Technology, Second Edition, pp. 198-200.
Derwent DB US 5,930,106, Jul. 1999.
Haller Gordon
Prall Kirk D.
Thakur Randhir P. S.
Huynh Yennhu B
Jr. Carl Whitehead
Micro)n Technology, Inc.
TraskBritt
LandOfFree
Method to form a corrugated structure for enhanced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to form a corrugated structure for enhanced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to form a corrugated structure for enhanced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3131689