Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-01-11
2001-02-06
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S279000, C438S283000, C438S585000, C438S275000
Reexamination Certificate
active
06184116
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a MOS gate electrode having a width not limited by photolithography resolution in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, photolithography and etching are used to form structures such as polysilicon gates, word lines, bit lines, local oxidation of silicon (LOCOS), shallow trench isolation (STI), and the like. A photoresist material is coated over the layer or layers to be etched. The photoresist material is exposed to actinic light through a mask, then developed to form the photoresist mask for etching the underlying layer or layers. Using optical lithography, a resolution as small as 0.13 microns can be achieved. For smaller feature sizes, electron beam or X-ray lithography is necessary. However, these types of photolithography are expensive and time-consuming. It is desired to find a way to achieve a controllable gate electrode having a width not limited by photolithographic resolution.
U.S. Pat. No. 5,597,764 to Venkatesan et al teaches a method of forming a self-aligned gate within a recess. U.S. Pat. No. 5,734,185 to Ignuchi et al discloses a method of forming a polysilicon gate between dielectric spacers. U.S. Pat. No. 5,667,632 to Burton et al teaches forming and removing a dielectric spacer and forming a polysilicon gate within the spacer recess. U.S. Pat. No. 5,202,272 to Hsieh et al shows a gate process where a polysilicon layer is etched to form a spacer. There is a silicon nitride layer over the spacer. U.S. Pat. No. 4,419,809 to Riseman et al also discloses a poly spacer method including multiple oxidations and a masked etching process. U.S. Pat. No. 4,931,137 to Sibuet teaches forming poly spacers on a block which is then removed to leave poly gates. U.S. Pat. No. 5,593,813 to Kim shows a microscopic patterning process. U.S. Pat. No. 5,705,414 to Lustig shows a poly spacer on a stepped TEOS layer used as a mask to etch an underlying poly layer. U.S. Pat. No. 5,916,821 to Kerber teaches silicon nitride spacers on TEOS as a mask to etch a poly layer. U.S. Pat. No. 5,923,981 to Qian teaches spacers used as a mask to etch poly. U.S. Pat. No. 5,663,590 to Kapoor shows a process where metal spacers are used to connect overlying metal lines.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for forming structures having small line width feature sizes in the fabrication of integrated circuits.
It is a further object of the invention to form MOS gate electrodes having small line width feature sizes.
A still further object of the invention is to form MOS gate electrodes having small line width feature sizes not limited by photolithographic resolution.
Yet another object of the invention is to form MOS gate electrodes having a line width controlled by spacer width.
Yet another object is to form a feature, such as a gate electrode, having a feature size, or a line width, controlled by spacer width and not limited by photolithographic resolution.
A further object is to integrate the formation of features having small line widths not limited by photolithographic resolution with the formation of features using conventional photolithographic processes.
In accordance with the objects of the invention, a new method for forming a feature, such as a gate electrode, having a feature size, or a line width, controlled by spacer width and not limited by photolithographic resolution is achieved. A dielectric stack is provided on the surface of a semiconductor substrate. The dielectric stack is etched away where it is not covered by a mask wherein the remaining dielectric stack has a width equal to the spacing between two of the gate electrodes to be formed. A gate oxide layer is grown on the surface of the semiconductor substrate not covered by the dielectric stack. A polysilicon layer is deposited overlying the gate oxide layer and the dielectric stack. The polysilicon layer is etched back to leave spacers on the sidewalls of the dielectric stack. A dielectric layer is deposited overlying the substrate and polished back whereby an upper portion of the dielectric stack and spacers are polished away. The remaining dielectric layer and the dielectric stack are removed whereby the spacers remain forming gate electrodes having the gate oxide layer thereunder to complete fabrication of gate electrodes in the manufacture of an integrated circuit device.
Also, in accordance with the objects of the invention, a process for integrating the formation of features having small line widths not limited by photolithographic resolution with the formation of features using conventional photolithographic processes is achieved. A dielectric stack is provided on the surface of a semiconductor substrate. The dielectric stack is etched away where it is not covered by a mask wherein the remaining dielectric stack has a width equal to the spacing between two of the narrow gate electrodes to be formed. A gate oxide layer is grown on the surface of the semiconductor substrate not covered by the dielectric stack. A polysilicon layer is deposited overlying the gate oxide layer and the dielectric stack. A first mask is formed over the polysilicon layer where wide gate electrodes are to be formed. The polysilicon layer not covered by the first mask is etched back to leave spacers on the sidewalls of the dielectric stack. Thereafter, the first mask is removed. A dielectric layer is deposited overlying the substrate and polished back whereby an upper portion of the dielectric stack and the spacers are polished away. The remaining dielectric layer and dielectric stack are removed whereby the spacers remain forming narrow gate electrodes having the gate oxide layer thereunder. A second mask is formed covering the narrow gate electrodes and forming a pattern over the polysilicon layer for forming wide gate electrodes. The polysilicon layer not covered by the second mask is patterned to form wide gate electrodes to complete integration of the fabrication of both narrow and wide gate electrodes in the manufacture of an integrated circuit device.
REFERENCES:
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4931137 (1990-06-01), Sibuet
patent: 5202272 (1993-04-01), Hsieh et al.
patent: 5593813 (1997-01-01), Kim
patent: 5663590 (1997-09-01), Kapoor
patent: 5667632 (1997-09-01), Burton et al.
patent: 5705414 (1998-01-01), Lustig
patent: 5734185 (1998-03-01), Iguchi et al.
patent: 5736435 (1998-04-01), Venkatesan et al.
patent: 5866934 (1999-02-01), Kadosh et al.
patent: 5916821 (1999-06-01), Kerber
patent: 5923981 (1999-07-01), Qian
patent: 5950091 (1999-09-01), Fulford, Jr. et al.
patent: 6066534 (2000-05-01), Son
patent: 6124174 (2000-09-01), Gardner et al.
Chang Kwan-Hwa
Lin Yu-Lun
Shen Yun-Hung
Ackerman Stephen B.
Pham Long
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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