Method to fabricate self-aligned dual damascene structures

Details Method to fabricate self-aligned dual damascene structures Method to fabricate self-aligned dual damascene structures

1999-05-25

2001-04-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S618000

Reexamination Certificate

active

06211063

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to a method to fabricate self-aligned dual damascene structures in the manufacture of integrated circuits.
(2) Description of the Prior Art
At integrated circuit feature sizes of 0.18 microns and below, it becomes advantageous to construct metal connections out of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.
The disadvantage of copper, however, is that it is more difficult to reliably etch than aluminum. To create copper traces, therefore, an alternative design approach is used. For conventional aluminum processing, metal is first deposited over a relatively flat surface and then patterned and etched to create connective traces. Alternatively, in copper processing, trenches are first cut into the isolation dielectric material where connective traces are planned. Then the metal is deposited to fill the traces. A polishing process is then used to etch back any overfill of metal in the trenches. This approach of inlaying metal into trenches to form features in the metal layer is called a damascene process.
An extension of the damascene process is to use it to form upper metal layers and to connect such layers to lower metal layers through dual damascene vias. First, two trenches are formed in a stack with the upper trench of larger width than the lower trench. Then both trenches are filled in a single metal deposition. By selecting the trench isolation materials appropriately, the selectivity of reactive ion etch (RIE) processes can be advantageously used to make these dual damascene vias self-aligning. This approach allows very small lower metal line widths to be reliably connected to upper level metal features.
Referring to
FIG. 1
, a cross-section of a partially completed prior art self-aligned dual damascene structure is shown. A substrate layer
10
is depicted. The substrate layer
10
encompasses all underlying layers, devices, junctions, and other features that have been formed prior to the deposition and definition of the first metal layer
12
. A first dielectric layer
14
, typically composed of silicon oxynitride, has been deposited overlying the substrate
10
and the first metal layer
12
. A first low k-value dielectric
16
, typically composed of fluorinated silicate glass (FSG), has been deposited overlying the first dielectric
14
. A low k-value dielectric is used in semiconductor processing to reduce the capacitive coupling of metal layers. Next, a second dielectric layer
18
, typically composed of silicon oxynitride has been deposited overlying the lower k-value dielectric
16
. The second dielectric layer
18
has been patterned and etched to create openings directly above the underlying first metal traces
12
. A second low k-value dielectric layer
20
, typically composed of an organic spin-on material such as hydrogen silsesquioxane (HSQ), has been deposited overlying the second dielectric layer
18
. A third dielectric layer
22
, composed of silicon oxide, has been deposited overlying the second low k-value dielectric
20
. A photoresist layer
24
has been deposited overlying the third dielectric layer
22
. Openings have been etched in the photoresist directly above the underlying metal traces
12
.
As is shown in
FIG. 1
, the upper opening in the photoresist layer
24
is wider than the lower opening in the second dielectric layer
18
. In subsequent processing, such upper trenches would be etched through the third dielectric layer
22
and the second low k-value layer
20
. Lower trenches would then be etched through the first low k-value layer
16
. If the RIE chemistry was selected properly, the second dielectric layer
18
would act as an etch stop for the upper trench etch. Likewise, the first dielectric layer
14
would act as an etch stop for the lower trench etch. A final etch to remove the remaining first dielectric layer would then expose the top surface of the first metal traces. After the two trenches are etched, a second metal layer of copper would then be deposited and etched back to finish the structure.
The dual damascene trench process described is called self-aligned. This process is self-aligned because, even if the trenches are misaligned to the underlying first metal traces, a careful final etch of the first dielectric layer will still create a working trench for metal deposition without creating shorts or voids.
Referring again to
FIG. 1
, a problem in the prior art is depicted. The RIE chemistry typically used for etching FSG layers is comprised of the gases C
4
F
8
, CO, and Ar. When HSQ is used to form the second low k-value layer
20
, this RIE chemistry will not etch properly. In fact the HSQ acts as an etch stop, and HSQ residue is left not etched as is shown by
26
.
One approach to improving the etch of a second low k-value layer
20
composed of HSQ is to add oxygen to the RIE etch chemistry such that the chemistry is comprised of the gases C
4
F
8
, CO, Ar, and O
2
. This alternative does eliminate the HSQ etch stop but it creates a new problem shown in FIG.
2
. The HSQ layer
20
etch profile reveals a bow or concave shape
28
. This bowing is especially pronounced once the photoresist layer
24
is stripped. The bowing profile presents a very difficult metal step coverage profile for the deposited copper layer.
Several prior art approaches attempt to use HSQ and other low k-value spin-on glass (SOG) materials to reduce line capacitance in integrated circuits. U.S. Pat. No. 5,818,111 to Jeng et al teaches layering HSQ or other low k-value dielectrics with silicon dioxide layers to improve the stability and reliability of the HSQ layers. U.S. Pat. No. 5,565,384 to Havemann teaches the use of organic SOG to lower line capacitance and to act as an etch stop below silicon dioxide to facilitate various self-aligned via designs. U.S. Pat. No. 5,607,773 to Ahlburn et al discloses a method to form an intermetal dielectric composite of oxide-HSQ-oxide where the HSQ reduces the dielectric constant. U.S. Pat. No. 5,728,630 to Nishimura et al teaches a method to form an interlayer film using silicone ladder polymers with HSQ.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits with dual damascene structures.
A further object of the present invention is to provide a method of fabricating dual damascene structures with intermetal layers of HSQ, silicon dioxide, and FSG.
A yet further object of the present invention is to provide a method of fabricating dual damascene structures with intermetal layers of HSQ, silicon dioxide, and FSG where the problem of HSQ etch stop is eliminated.
Another yet further object of the present invention is to provide a method of fabricating dual damascene structures with intermetal layers of HSQ, silicon oxynitride, and FSG where the problem of HSQ etch profile bowing is eliminated.
Another object of the present invention is to provide a method of fabricating integrated circuits with self-aligned dual damascene vias.
Another object of the present invention is to provide a method of fabricating integrated circuits with dual damascene structures using a single RIE etch run with a two tep etch recipe comprising first an etch chemistry of C
4
F
8
, CO, Ar, and N
2
and second an etch chemistry of C
4
F
8
, CO, and Ar.
In accordance with the objects of this invention, a new method of fabricating an integrated circuit with dual damascene structures is achieved. A substrate layer is provided encompassing all underlying layers, devices, junctions, and other features that are formed prior to the deposition of a first metal layer. The first metal layer is etched to define conductive traces. A first silicon oxynitride layer is deposited overlying the substrate and the first metal layer. A low k-value dielectric of fluorinated silicate glass (FSG)

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