Method to fabricate patterned strain-relaxed SiGe epitaxial...

Details Method to fabricate patterned strain-relaxed SiGe epitaxial... Method to fabricate patterned strain-relaxed SiGe epitaxial...

2008-03-11

2008-03-11

Smoot, Stephen W. (Department: 2813)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Fluid growth from gaseous state combined with preceding...

C257SE21103

Reexamination Certificate

active

07341929

ABSTRACT:
A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer are deposited. According to the disclosure, an active area and a non-active area are defined through ion-implanting. Therefore, the threading dislocation occurring in the active area concentrates in the non-active area, and the density of the threading dislocation is lowered. Furthermore, the performance of the semiconductor is also enhanced.

REFERENCES:
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patent: 2006/0022200 (2006-02-01), Shiono et al.
S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, 2ndedition, Lattice Press, 2000, pp. 488-489.

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