Method to fabricate elevated source/drain transistor with...

Details Method to fabricate elevated source/drain transistor with... Method to fabricate elevated source/drain transistor with...

2002-08-16

2004-08-24

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S514000, C438S556000, C257S288000, C257S412000

Reexamination Certificate

active

06780691

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an elevated source/drain transistor structure having a large area for silicidation in the fabrication of integrated circuits.
(2) Description of the Prior Art
The utilitarian features in forthcoming semiconductor devices are small gate dimensions and shallow source/drain junctions. As we await the maturity and development of compatible techniques to assure shallow junctions with high dopant activation for a lower Schottky barrier between metallic contact and doped silicon, we may require raised or elevated source/drain features to fan out current crowding and lower the series resistance.
New techniques of making elevated source/drain features are being proposed. U.S. Pat. No. 6,090,691 to Ang et al discloses damascene gate and source/drain process with raised polysilicon source/drain regions. U.S. Pat. No. 6,207,517 to Muller teaches a raised polysilicon source/drain process. U.S. Pat. No. 5,271,132 to Xiang et al shows raised source/drain contacts. U.S. Pat. No. 6,090,672 to Wanless shows a metal gate process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming a transistor having elevated source/drain structures.
A further object of the invention is to provide a method of forming a transistor having an elevated source/drain structure and a large silicon area for silicidation.
Yet another object is to provide a method of forming a transistor having an elevated source/drain structure with a large area for silicidation wherein the source/drain structure may be doped polysilicon or a metal.
In accordance with the objects of this invention a method for forming a transistor having an elevated source/drain structure is achieved. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions and wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.
Also in accordance with the objects of this invention a MOSFET device having an elevated source/drain structure is achieved. A gate electrode overlies a substrate, isolated from the substrate by a gate dielectric layer. Isolation regions lie in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Source/drain extensions in the substrate lie between the isolation regions and the gate electrode. Elevated source/drain junctions overlie the substrate adjacent to the gate electrode and separated from the gate electrode by dielectric spacers wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby increasing the area of the elevated source/drain junctions.


REFERENCES:
patent: 5539229 (1996-07-01), Noble, Jr et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 6090672 (2000-07-01), Wanlass
patent: 6090691 (2000-07-01), Ang et al.
patent: 6207517 (2001-03-01), Muller
patent: 6271132 (2001-08-01), Xiang et al.
patent: 6333247 (2001-12-01), Chan et al.

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