Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Implanting to form insulator
Reexamination Certificate
2008-06-10
2008-06-10
Pham, Thanhha S. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Implanting to form insulator
C438S404000, C438S766000, C257SE21248
Reexamination Certificate
active
07384857
ABSTRACT:
The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.
REFERENCES:
patent: 5438015 (1995-08-01), Lur
patent: 5466630 (1995-11-01), Lur
patent: 5468657 (1995-11-01), Hsu
patent: 5841171 (1998-11-01), Iwamatsu et al.
patent: 6069054 (2000-05-01), Choi
patent: 6191008 (2001-02-01), So
patent: 6249026 (2001-06-01), Matsumoto et al.
patent: 6362070 (2002-03-01), Villa et al.
patent: 6506662 (2003-01-01), Ogura et al.
patent: 6593637 (2003-07-01), Ibok
patent: 6869867 (2005-03-01), Miyashita et al.
“Characteristics of MOS Capacitors of BF2or B Implanted Polysilicon Gate with and without POC13Co-doped”, J.C. Hsieh, et al.,IEEEElectron Device Letters, vol. 14, No. 5, May 1993, pp. 222-224.
“The Effect of Fluorine in Silicon Dioxide Gate Dielectrics”, P. J. Wright, et al.,IEEETransactions on Electron Devices, vol. 36, No. 5, May 1989, pp. 879-889.
Haro Rosalio
Pham Thanhha S.
Seiko Epson Corporation
LandOfFree
Method to fabricate completely isolated silicon regions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to fabricate completely isolated silicon regions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to fabricate completely isolated silicon regions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2808601