Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2000-05-08
2001-07-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S151000, C438S165000, C438S284000, C438S586000, C257S347000, C257S355000, C257S546000, C257S757000
Reexamination Certificate
active
06265251
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming thick oxide MOS transistors for electrostatic discharge protection in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Electrostatic discharge (ESD) robustness for CMOS technology has always been a difficult challenge. In larger feature size CMOS processes, thick oxide devices, such as the field oxide device (FOD) or the metal gate over field oxide device (MGFO), have been used to provide ESD protection for integrated circuit inputs. With the advent of sub-micron feature sizes, new approaches to ESD protection have become necessary.
Referring to
FIG. 1
, an input pad
10
is shown for a prior art CMOS integrated circuit. The input pad
10
in this application is connected to an inverter-buffer
18
. To protect the transistors of the inverter-buffer
18
from ESD events, a field oxide device (FOD)
14
is fabricated on the circuit in the input path. The FOD transistor
14
is designed to perform several functions. First, if the FOD transistor
14
is an n-channel device, there is p-n diode between the substrate and the drain of the FOD. This will effectively clamp negative voltages to one diode drop below the substrate voltage. Second, and more importantly, the FOD device
14
is designed to shunt positive voltage spikes, such as during an ESD event, to the substrate while protecting the inverter-buffer
18
.
Two features enable the FOD transistor
14
to protect against ESD events while not being destroyed in the process. First, the FOD transistor
14
is specially designed to have a large voltage threshold (V
t
). The FOD transistor
14
may be formed with either a polysilicon or metal gate. Unlike typical transistors, which have gate electrodes formed over very thin oxide, the FOD electrode is formed over a section of very thick field oxide. Since V
t
is proportional to the thickness of the gate oxide, V
t
for the FOD
14
is relatively large (15 V to 30 V) compared to that of the logic transistors of the inverter-buffer
18
(around 0.7 V). The large voltage threshold means that the FOD transistor is an open circuit for all expected input voltages excepting ESD events.
The second feature of the FOD transistor
14
is its performance during the ESD event. Under ESD stress conditions, the FOD behavior changes drastically from normal MOS operation. The conduction mechanism changes to a parasitic lateral bipolar device. Normal MOS channel conduction does not have the capability of carrying amps of current. The onset of bipolar action is determined by the avalanche breakdown of the n+ drain diffusion with the generation of electron-hole pairs. The generated electrons are swept across the drain towards the drain contact, adding to the drain current. The generated holes drift towards the substrate contact thereby giving rise to a substrate current similar to the base current of the bipolar transistor. As substrate current increases, the potential at the source-substrate junction increases to the point of forward-biasing this junction and causing electrons to be emitted into the substrate. When the electron current density from the source begins to contribute to the drain current, the parasitic bipolar transistor may be considered to be turned on. This is called snapback.
Once the lateral bipolar transistor turns on, the operating mechanism of the device is similar to that of an npn bipolar transistor. The drain voltage decreases. A negative resistance region is observed due to the availability of more carriers for multiplication until a minimum voltage is reached. A gate is not necessary for npn snapback to take place. However, in the FOD, the gate voltage can change the silicon surface potential and thereby reduce the source (emitter) barrier to turn on the npn device. The npn device turns on at a lower level to protect the thin gate oxide of the inverter-buffer
18
.
Referring now to
FIG. 2
, a cross section of a prior art FOD transistor is shown. Field oxide regions
24
are formed in the substrate
20
. Source junctions
32
and drain junctions
28
are formed in the substrate. The gate electrode
44
is formed by the metal layer
40
overlying field oxide region
24
between the source junction
32
and the drain junctions
28
. The gate electrode
44
and the drain
48
are then connected to the input pad while the source
52
is connected to the circuit ground (VSS).
Sub-micron CMOS processes cause two problems for the prior art FOD approach. First, many new processes no longer have the field oxide layer formed by local oxidation of silicon (LOCOS). Shallow trench isolation (STI) has replaced LOCOS for isolation region definition. A controllable channel cannot be created under the STI structure. Even if a sub-micron process is not using STI, the shallowness of the junctions necessary to produce sub-micron transistors is a second problem. If very shallow source or drain junctions are used for the FOD, the threshold voltage is lowered. In addition, the device is easily damaged due to concentration of heating during the secondary breakdown event.
Several prior art approaches disclose methods to improve ESD performance of an integrated circuit device. U.S. Pat. No. 5,618,740 to Huang discloses a process to create CMOS outputs that have enhanced ESD resistance. CMOS output transistors do not receive the anti-punch through pocket implant as do core CMOS devices. The absence of the pocket junctions increases the ESD performance of the output transistors. U.S. Pat. No. 5,872,378 to Rose et al teaches an ESD protection network for non-volatile memory circuits. U.S. Pat. No. 5,929,493 to Wu discloses a process for forming CMOS transistors with self-aligned planarization twin well while using fewer masks. A boron blanket implant is included that will increase the threshold of the field oxide device.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form thick oxide MOS transistors for electrostatic discharge protection in the manufacture of integrated circuits.
Another object of the present invention is to provide a thick oxide MOS transistor device for electrostatic discharge protection in the manufacture of integrated circuits.
Another further object of the present invention is to provide a method of fabricating a thick oxide MOS transistor without a field oxidation layer.
Another further object of the present invention is to provide a method of fabricating a thick oxide MOS transistor that has deep well source and drain junctions to improve electrostatic discharge performance.
Another yet further object of the present invention is to provide a method to form a thick oxide MOS transistor without adding processing complexity.
In accordance with the objects of this invention, a new method of forming a thick gate oxide MOS transistor for electrostatic discharge protection in the manufacture of an integrated circuit device has been achieved. Shallow trench isolations are provided in a semiconductor substrate. Ions are implanted into the semiconductor substrate to form a first well and a second well. The first well forms the drain of the planned thick gate oxide MOS transistor. The second well forms the source of the planned thick gate oxide MOS transistor. A thin oxide layer is formed overlying the semiconductor substrate. A polysilicon layer is deposited overlying the thin oxide layer. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well and the second well to form a first lightly-doped region and a second lightly-doped region of the same type as the first well and the second well. The first and second lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates.
Ions are implanted into the first well and the second well to form a first heavily-doped region and a second heavily-dope
Jun Cai
Lo Keng Foo
Anya Igwe U.
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Smith Matthew
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