Method to fabricate a floating gate with a sloping sidewall...

Details Method to fabricate a floating gate with a sloping sidewall... Method to fabricate a floating gate with a sloping sidewall...

1999-03-29

2001-09-04

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S264000, C438S713000, C438S716000, C438S261000

Reexamination Certificate

active

06284637

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory structures, and more particularly, to the formation of a floating gate with a sloping sidewall for a Flash Memory Cell.
(2) Description of the Prior Art
Flash EEPROMs are a well-known class of semiconductor devices in the art. These devices are used in many digital circuit applications where binary data must be retained even if the application system power is removed. Further, these devices allow the data to be altered, or re-written, during normal operations.
EEPROM memory devices employ floating gates; that is Field Effect Transistor (FET) gates completely surrounded by an isolating layer such as silicon oxide. The presence of charge on these floating gates effectively shifts the threshold voltage of the FET. This effect can be detected by additional circuitry such that the charge state of the floating gate can be used to represent binary information. Specifically, FLASH EEPROM memories employ EEPROM cells in a configuration that allows for the bulk erasing, or flashing, of large blocks of memory cells in a normal circuit application without using any external data erasing source, such as ultra-violet light.
FIG. 1
shows a cross sectional view of a partially completed prior art EEPROM memory cell. The cell contains a substrate
11
typically composed of lightly P- doped monocrystalline silicon. Isolation regions
12
extend above and below the substrate surface to effectively isolate this memory cell from surrounding cells. The region defined along the substrate surface between the two isolation regions
12
is called the active region. A tunneling oxide layer
13
overlays the substrate
11
and the isolation regions
12
. A polysilicon floating gate
14
overlays the tunneling oxide
13
. The tunneling oxide
13
serves as an isolator between the floating gate
14
and the substrate
11
. An interpoly dielectric film
15
, typically comprised of oxide-nitride-oxide, or ONO, overlays the floating gate
14
. Another layer of polysilicon forms the control gate
16
of the memory cell. The interpoly dielectric film
15
serves as an isolator between the control gate
16
and the floating gate
14
. The overlaying layers of control gate
16
, interpoly dielectric
15
, floating gate
14
, and tunneling oxide
13
over substrate
11
form a stacking gate structure.
Data is stored in the EEPROM cells by the storage of a charge on the floating gate
14
. Because this gate
14
is electrically isolated from both the substrate
11
and the control gate
16
, a charge can be stored for indefinite periods without any voltage applied to the gate
14
. To charge or write data to the floating gate
14
, a voltage must be applied from the control gate
16
to the substrate
11
. This voltage is divided across the capacitor formed by the control gate
16
, the interpoly dielectric
15
, and the floating gate
14
, and the capacitor formed by the floating gate
14
, the tunneling oxide
13
, and the substrate
11
. If the voltage from the floating gate
14
to the substrate
11
is large enough, charge movement will occur as electrons tunnel from the substrate
11
to the floating gate
14
through the tunneling oxide layer
13
. When the voltage from control gate
16
to substrate
11
is reduced or removed, the charge is trapped on the floating gate
14
and the data is retained in the memory cell. The presence of this charge increases the threshold voltage of the memory cell FET, and this can be detected by a cell sense circuit.
A prominent feature of the prior art cell shown in
FIG. 1
is severe topology introduced by the field oxide
12
isolation. Because the polysilicon floating gate
14
overlaps this isolation
12
, as well as the tunneling oxide layer
13
, all of the subsequent layers of material reflect this topology. Notably, a sharp corner exists at the polysilicon floating gate edge
18
. This sharp corner causes problems with the integrity of the interpoly dielectric
15
. The effective breakdown probability of the interpoly dielectric is increased, as is the amount of charge leakage between the floating gate
14
and the control gate
16
. The effect of this charge leakage is the performance of the slash memory cell is deteriorated. As charge leaks off the floating gate
14
, the effective threshold voltage of the memory cell FET is altered, compromising the data held on the cell.
A prior art attempt to reduce the sharpness of the floating gate edge is taught in U.S. Pat. No. 5,635,416 to Chen et al. Chen et al teaches the formation of tunnel oxide and the first part of the floating gate polysilicon prior to the formation of the isolation oxide. The second part of the floating gate extends on to the isolation oxide. U.S. Pat. No. 5,573,979 to Tsu et al shows a sloped polysilicon sidewall for a memory device. However, Tsu is directed at capacitor electrodes and teaches a sloping sidewall method for what are termed unreactive and barrier layers such as platinum and titanium nitride, respectively, in the formation of three-dimensional capacitor nodes for DRAM. U.S. Pat. No. 5,554,564 to Nishioka et al shows a method of rounding the bottom capacitor electrode through the oxidation of the noble metals used.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a floating gate structure for a Flash EEPROM cell.
Another object of the present invention is to provide an effective and very manufacturable method of fabricating a floating gate structure for a Flash EEPROM device having an improved profile and performance.
Yet another object of the present invention is to provide an effective and manufacturable floating gate structure for a Flash EEPROM device.
In accordance with the objects of this invention, a new method of fabricating floating gates for Flash EEPROM devices having an improved profile and performance is achieved. A semiconductor substrate is provided. Field oxide regions are formed in this substrate. A tunneling oxide layer is provided overlying both the substrate and the field oxide regions. A first polysilicon layer is deposited overlying the tunneling oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is patterned and etched leaving the photoresist layer where the floating gates are to be defined. The photoresist layer, the first polysilicon layer and the tunneling oxide are specially etched to both define the floating gate structures and to create non-vertical, sloping sidewalls. The remaining photoresist layer is removed. An interpoly dielectric is deposited overlying the floating gates and the rest of the wafer. A second polysilicon layer is deposited overlying the interpoly dielectric completing the fabrication of the floating gates for the Flash/EEPROM devices.
Also in accordance with the objects of this invention, a floating gate for a Flash EEPROM device having an improved profile and performance is achieved. Field oxide isolations define active areas in the semiconductor substrate. A tunneling oxide overlies the semiconductor substrate. A polysilicon floating gate with non-vertical, sloping sidewalls overlies the tunneling oxide. An interpoly dielectric overlies the polysilicon layer. A control gate of polysilicon overlies the interpoly dielectric to complete the floating gate structure for the Flash EEPROM device.


REFERENCES:
patent: 5554564 (1996-09-01), Nishioka et al.
patent: 5573979 (1996-11-01), Tsu et al.
patent: 5635416 (1997-06-01), Chen et al.
patent: 5830807 (1998-11-01), Matsunaga et al.
patent: 5973353 (1999-10-01), Yang et al.
patent: 6051451 (2000-04-01), He et al.
patent: 6063668 (2000-05-01), He et al.
Wolf et al., “Silicon Processing for the VLSI Era vol. 1: Process Technology”, Lattice Press, pp. 551-554, 1986.*
Wolf et al., Silicon Processing for the VLSI Era vol. 1: Process Technology, pp. 547-549, 1986, Lattice Press.

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