Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-16
2002-12-17
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S316000
Reexamination Certificate
active
06495880
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory structures, and more particularly, to the formation of Flash Electically Erasable Programmable Read Only Memories (EEPROM) with a planar stacked gate.
(2) Description of the Prior Art
Flash EEPROMs are a well-known class of semiconductor devices in the art. These devices are used in many digital circuit applications where binary data must be retained even if the application system power is removed. Further, theses devices allow the data to be altered, or re-written, during normal operations.
EEPROM memory devices employ floating gates; that is Field Effect Transistor (FET) gates completely surrounded by an isolating layer such as silicon oxide. The presence of charge on these floating gates effectively shifts the threshold voltage of the FET. This effect can be detected by additional circuitry such that the charge state of the floating gate can be used to represent binary information. Specifically, FLASH EEPROM memories employ EEPROM cells in a configuration that allows for the bulk erasing, or flashing, of large blocks of memory cells in a normal circuit application without using any external data erasing source, such as ultra-violet light.
FIG. 1
shows a cross sectional view of a partially completed prior art EEPROM memory cell. The cell contains a substrate
11
typically composed of lightly P-doped monocrystalline silicon. Isolation regions
12
extend above and below the substrate surface to effectively isolate this memory cell from surrounding cells. The region defined along the substrate surface between the two isolation regions
12
is called the active region. A tunneling oxide layer
13
overlays the substrate
11
and the isolation regions
12
. A polysilicon floating gate
14
overlays the tunneling oxide
13
. The tunneling oxide
13
serves as an isolator between the floating gate
14
and the substrate
11
. An interpoly dielectric film
15
of oxide-nitride-oxide, or ONO, overlays the floating gate
14
. Another layer of polysilicon forms the control gate
16
of the memory cell. The interpoly dielectric film
15
serves as an isolator between the control gate
16
and the floating gate
14
. The overlaying layers of control gate
16
, interpoly dielectric
15
, floating gate
14
, and tunneling oxide
13
over substrate
11
form a stacking gate structure. Additional layers that are not shown include the typical N+ buried layer bit lines, metal layers used for connectivity, inter-metal dielectrics, and passivations.
Data is stored in the EEPROM cells by the storage of a charge on the floating gate
14
. Because this gate
14
is electrically isolated from both the substrate
11
and the control gate
16
, a charge can be stored for indefinite periods without any voltage applied to the gate
14
. To charge or write data to the floating gate
14
, a voltage must be applied from the control gate
16
to the substrate
11
. This voltage is divided across the capacitor formed by the control gate
16
, the interpoly dielectric
15
, and the floating gate
14
, and the capacitor formed by the floating gate
14
, the tunneling oxide
13
, and the substrate
11
. If the voltage from the floating gate
14
to the substrate
11
is large enough, charge movement will occur as electrons tunnel from the substrate
11
to the floating gate
14
through the tunneling oxide layer
13
. When the voltage from control gate
16
to substrate
11
is reduced or removed, the charge is trapped on the floating gate
14
and the data is retained in the memory cell. The presence of this charge increases the threshold voltage of the memory cell FET, and this can be detected by a cell sense circuit.
A prominent feature of the prior art is severe topology introduced by the field oxide
12
isolation. Because the polysilicon floating gate
14
overlaps this isolation
12
, as well as the tunneling oxide layer
13
, all of the subsequent layers of material reflect this topology.
This severe topology affects the stacking gate structure in the several adverse ways. First, the effective thickness L
1
of the stacking gate in the center of the active region is different from the effective thickness L
2
of the stacking gate near the isolation, region.
Second, the severe topology increases the occurrence and severity of polysilicon residue remaining between polysilicon traces after photolithographic etching. This can cause shorting between adjacent floating gates
14
and between adjacent control gates
16
. Polysilicon residue also causes poor interpoly dielectric quality.
The third problem caused by the severe topology is active region trenching. As can be seen in the cross-sectional illustration, a lowered trench is formed over the active region due to the topology of the field oxide, isolation
12
.
Prior art attempts to reduce the severe topology in the stacking gate caused by the field oxide isolation, have utilized a Chemical Mechanical Polishing (CMP) process after polysilicon floating gate deposition to plane the polysilicon layer. U.S. Pat. No. 5,643,813 to Acocella et al discloses a high density Flash EEPROM having an improved floating gate self-aligned process and teaches the use of a nitride layer over a recessed oxide to act as an etch stop for the polysilicon CMP step. U.S. Pat. No. 5,753,525 to Hsu et al shows an EEPROM with an improved coupling ratio. U.S. Pat. No. 5,739,566 to Ota shows a memory cell with self-aligned contacts. U.S. Pat. No. 5,635,415 to Hong shows a method for forming a buried bit line Flash EEPROM.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a stacked gate Flash EEPROM device.
Another object of the present invention is to provide an effective and very manufacturable method of fabricating a stacked gate Flash EEPROM device having an improved stacked layer topology.
In accordance with the objects of this invention, a new method of fabricating a stacked gate Flash EEPROM device having an improved stacked layer topology is achieved. A semiconductor substrate is provided. Field oxide regions are formed in this substrate. A tunneling oxide layer is provided on the entire substrate surface. A first polysilicon layer is deposited overlying the tunneling oxide layer. This first polysilicon layer is polished away until it is flat, without exposing the tunneling oxide, field oxide, or substrate underlying the first polysilicon layer. The first polysilicon is then etched to define the floating gate. Source and drain regions associated with the floating gate are formed within the semiconductor substrate. An interpoly dielectric is deposited overlying the planar first polysilicon layer and the oxide layer. A second polysilicon layer is deposited overlying the interpoly dielectric. The second polysilicon layer and interpoly dielectric are then etched to define the control gate overlying the floating gate. An insulating layer is deposited overlying the control gate and the oxide layer. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
Also in accordance with the objects of this invention, a stacked gate Flash EEPROM device having an improved stacked layer topology is described. Field oxide isolations define active areas in the semiconductor substrate. A tunneling oxide overlies the semiconductor substrate. A polysilicon floating gate overlies the tunneling oxide. This polysilicon layer, where defined, has a flat topology. Source and gate regions lie within the semiconductor substrate. An interpoly dielectric overlies the polysilicon layer. A control gate of polysilicon overlies the interpoly dielectric. An insulating layer overlies the semiconductor substrate and the control gate. A patterned metal layer overlies the insulating layer and extends through co
Chen Jong
Jung Lin Chrong
Kuo Di-Son
Su Hung-Der
Huynh Andy
Schnabel Douglas R
Taiwan Semiconductor Manufacturing Company
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