Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2003-11-20
2004-12-28
Thai, Luan (Department: 2829)
Semiconductor device manufacturing: process
Making passive device
C438S421000, C438S422000
Reexamination Certificate
active
06835631
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of enhancing the performance of inductors.
BACKGROUND OF THE INVENTION
The quality factor (Q factor) is affected by capacitance loss due to coupling to underlying metals and substrate loss due to eddy current.
U.S. Pat. No. 6,180,995 B1 to Herbert describes an air gap under a field oxide under inductors.
U.S. Pat. No. 6,307,247 B1 to Davies describes an inductor process with low-k layers.
U.S. Pat. No. 6,287,979 B1 to Zhou et al. describes an air gap process between conductive lines.
U.S. Pat. No. 4,634,494 to Taji et al. describes a process to selectively etch a doped oxide layer.
U.S. Pat. No. 5,742,091 to Hébert describes a semiconductor device within which parasitic capacitances are minimized and a method of fabricating same.
U.S. Pat. No. 6,303,423 to Lin describes a method for forming high performance system-on-chip using post passivation process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide improved methods of fabricating inductor devices with reduced capacitance loss.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.
REFERENCES:
patent: 4634494 (1987-01-01), Taji et al.
patent: 5742091 (1998-04-01), Hebert
patent: 6180995 (2001-01-01), Hebert
patent: 6287979 (2001-09-01), Zhou et al.
patent: 6303423 (2001-10-01), Lin
patent: 6307247 (2001-10-01), Davies
patent: 6495903 (2002-12-01), Xu et al.
Chan Lap
Chu Sanford
Hwei Ng Chit
Verma Purakh Raj
Zhen Zheng Jia
Chartered Semiconductor Manufacturing Ltd
Stanton Stephen G.
Thai Luan
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