Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2000-07-19
2002-10-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S026000, C438S106000, C438S108000, C438S127000, C257S738000, C257S778000
Reexamination Certificate
active
06468832
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits. More specifically, the invention relates to enclosing integrated circuits.
BACKGROUND OF THE INVENTION
Commonly assigned, U.S. patent application Ser. No. 09/006,759 entitled “A Semiconductor Wafer Having A Bottom Surface Protective Coating”, by Kao et al., filed on Jan. 14, 1998, discloses providing a protective coating on a bottom surface of a semiconductor die. In Kao et al., a wafer for flip-chips or surface mount dice is coated on a back side with an epoxy and cured. One of the features of the protective coating is to provide protection from light-induced bias. Such a protective coating does not cover the side of a die. Processing of surface mount dice may make it difficult to provide a protective coating that is opaque.
The micro surface mount die is an extension of flip chip technology where solder bumps on die pads are the means to make electrical connections between the die and a PC board. Thus, the micro surface mount die (SMD) is a true chip size package where the die is the package.
Micro SMD wafers go through normal wafer fabrication processes except that the die pads are redistributed to create a standard pattern of the bumps. Bumps are then provided on the die pads. After the bumping process is completed, the back of the wafer may be coated with epoxy and cured. The wafer may then be singulated to form bumped dice.
To facilitate discussion,
FIG. 1
is a cross-sectional view of a singulated micro surface mount die
10
with a bottom surface coating
12
. Solder balls
14
have been mounted to the top side of the surface mount die
10
.
Commonly assigned, U.S. patent application Ser. No. 09/359,074, entitled “Techniques For Wafer Level Molding Of Underfill Encapsulant”, by Luu Nguyen et al., filed Jul. 22, 1999, discloses the placing of an encapsulant on a plurality of flip chips in a wafer. The wafer is then singulated to provide protected flip chips. Such protection may not be provided on the sides of the singulated chip.
Other methods of protecting surface mounted dice may be provided by the use of underfill or glob top processes. In an underfill process, underfill material is placed within a gap between a bumped device and a substrate. The gap may be small, and the underfill process may be slow. The resulting underfill process may not provide protection to the back side of the bumped die. The glob top process may be used to provide a plastic glob over a bumped device that has been mounted on a substrate. Using the glob top process on every mounted bumped device may slow the manufacturing process.
It would be desirable to provide protection for a bumped chip (flip chip or surface mount die) that provides protection on all sides of a bumped chip. It would also be desirable to provide a heat sink for a bumped chip.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a variety of techniques is provided for providing encapsulated bumped dice. Generally, singulated bumped dice are mounted on a die attach panel. The bumped dice and die attach panel are then encapsulated in a mold compound. The encapsulated dice are then singulated.
Another embodiment of the invention provides a die with partially flattened bumps connected to a die attach pad, where the die, die attach pad and part of the partially flattened bumps are encapsulated.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
REFERENCES:
patent: 5864174 (1999-01-01), Yamada et al.
patent: 6075290 (2000-06-01), Schaefer et al.
patent: 6093972 (2000-07-01), Carney et al.
patent: 6133634 (2000-10-01), Joshi
patent: 6157086 (2000-12-01), Weber
patent: 6204095 (2001-03-01), Farnworth
patent: 6245595 (2001-06-01), Nguyen et al.
National Semiconductor Corporation
Tran Mai-Huong
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