Method to detect NAND-flash parameters by hardware...

Details Method to detect NAND-flash parameters by hardware... Method to detect NAND-flash parameters by hardware...

2005-02-25

2010-02-02

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S218000, C713S001000, C713S002000

Reexamination Certificate

active

07657696

ABSTRACT:
A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.

REFERENCES:
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patent: 2003/0172261 (2003-09-01), Lee et al.
patent: 2004/0017708 (2004-01-01), Choi et al.
patent: 2005/0108500 (2005-05-01), Kishida et al.
“The Authoritative Dictionary of IEEE Standards and Terms” Seventh Edition, Standards Information Network IEEE Press, Copyright 2000 p. 168 and 264.
Andrew S. Tanenbaum “Structured Computer Organization”, 1999, Alan Apt, fourth edition, p. 8.
Samsung Electronics, 256M×8 Bit / 128M×16 Bit NAND Flash Memory, May 19, 2004.

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