Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-16
2001-06-26
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S677000, C438S674000, C427S301000, C427S304000, C427S305000
Reexamination Certificate
active
06251781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to the formation of damascene interconnects through the creation of platinum seed layers to selectively plate copper in the manufacture of integrated circuits.
2. Description of the Prior Art
As integrated circuit feature sizes continue to decrease, it has become advantageous to construct metal connections out of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.
The disadvantage of copper, however, is that it is more difficult to reliably etch than aluminum. To create copper traces, therefore, alternative design approaches such as damascene and dual damascene structures have been employed. By using damascene techniques, copper line etches are eliminated. Instead, trenches are first cut into the isolation dielectric material where connective traces are planned. Then the copper is deposited to fill the traces. A polishing process is used to etch back any overfill of copper in the trenches. In this way, damascene approaches allow the use of copper for interconnects.
Referring to
FIG. 1
, a cross-section of a partially completed prior art dual damascene structure is shown. A substrate layer
10
is depicted. The substrate layer
10
encompasses all underlying layers, devices, junctions, and other features that have been formed prior to the deposition and definition of the conductive traces
18
in the isolation layer
14
. A dielectric layer
22
overlies the isolation layer
26
and partially overlies the conductive traces
18
.
A via opening is shown formed in the dielectric layer
22
to expose the top surface of the conductive trace
18
. A trench is also formed in the dielectric layer
22
. A barrier layer
30
is deposited overlying the dielectric layer
22
and the exposed conductive traces
18
. The purpose of the barrier layer
30
is to prevent diffusion of the subsequently deposited copper into the conductive traces
18
or the dielectric layer
22
. Since the copper layer will be deposited using electroless plating, a seed layer
34
is deposited overlying the barrier layer
30
. The purpose of the seed layer
34
is to provide a thin layer of activation atoms to catalyze the electroless plating process. The seed layer
34
may be made up of copper, platinum, or palladium. The seed layer
34
is typically deposited by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process.
Referring to
FIG. 2
, the result of the electroless plating deposition of the copper layer
38
is shown. Assuming copper was used as the seed layer
34
, the seed layer
34
is absorbed into the copper layer
38
during the deposition process. Note that the copper layer
38
is deposited everywhere on the wafer overlying the barrier layer
30
. This universal deposition of the copper layer
38
is because the seed layer
34
was also deposited everywhere on the wafer. To form interconnect elements, both the excess copper layer
38
and the excess barrier layer
30
must be removed. This is typically accomplished by subjecting the wafers to a chemical mechanical polish (CMP).
Referring now to
FIG. 3
, during the CMP process, the copper layer
38
is polished down to a plug. An encapsulation layer
42
is deposited overlying the copper layer
38
to protect the copper from oxidation during subsequent processing steps.
It would be advantageous to eliminate the CMP process used to polish down the copper layer
38
in the prior art method. To do this, it is helpful to deposit the copper only where it is needed. Likewise, it would be advantageous to simplify, and make less expensive, the process used to form the seed layer
34
.
Several prior art approaches attempt to improve electroless plating processes for use in integrated circuit metalization. U.S. Pat. No. 5,674,787 to Zhao et al teaches a process to selectively deposit copper to form interconnect plugs. A copper ion seed layer is used to activate the electroless copper plating process. A dielectric layer is deposited and anisotropically etched to form a dielectric barrier on the sidewalls of the connective trench. An encapsulation layer is electroless plated over the copper plug. U.S. Pat. No. 5,723,387 to Chen discloses an apparatus and a process for forming copper interconnects. Platinum or palladium ions are used as the seed layer to activate the electroless plating of the copper layer. The copper layer is not selectively deposited and a post plating chemical mechanical polish must be done. U.S. Pat. No. 4,574,095 to Baum et al teaches a process to selectively deposit copper by formation of a palladium seed layer by photo-induced decomposition of gaseous complex at a wavelength of 249 nanometers. The electroless plated copper layer is then deposited where the palladium layer is so formed. U.S. Pat. No. 5,824,599 to Schacham-Diamond et al teaches a process to non-selectively deposit a copper layer by electroless plating. An aluminum layer is deposited overlying the copper seed layer to prevent oxidation of the seed layer prior to plating. U.S. Pat. No. 5,308,796 to Feldman et al discloses a process to selectively deposit a copper layer over a metal silicide layer. U.S. Pat. No. 4,692,349 to Georgiou et al discloses a process to electroless plate cobalt or nickel to form via plugs.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits with copper interconnects.
A further object of the present invention is to provide a method of fabricating copper interconnects by depositing copper using an electroless plating process.
Another further object of the present invention is to provide a method of fabricating copper interconnects where the copper layer is selectively deposited such that little or no excess copper needs to be removed by chemical mechanical polishing.
Yet another further object of the present invention is to provide a method of fabricating copper interconnects by selective electroless plating of copper catalyzed by a platinum seed layer that is deposited by photo-reduction of a solution of platinum ions.
In accordance with the objects of this invention, a new method of fabricating copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the platinum ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer. A passivation layer is deposited overlying the encapsulation layer to complete the fabrication of the integrated circuit device.
REFERENCES:
patent: 4574095 (1986-03-01), Baum et al.
patent: 4692349 (1987-09-01), Georgiou et al.
patent: 5308796 (1994-05-01), Feldman et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5723387 (1998-03-01), Chen
patent: 5824599 (1998-10-01), Schacham-Diamond et al.
patent: 5895261 (2000-07-01), Schinella et al.
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6087258 (2
Chan Lap
Xu Guo-Qin
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Ltd.
Everhart Caridad
Pike Rosemary L. S.
Saile George O.
Schnabel Doug
LandOfFree
Method to deposit a platinum seed layer for use in selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to deposit a platinum seed layer for use in selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to deposit a platinum seed layer for use in selective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2510826